496 lines
29 KiB
C
496 lines
29 KiB
C
/*!
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\file gd32f4xx_usart.h
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\brief definitions for the USART
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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*/
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/*
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F4XX_USART_H
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#define GD32F4XX_USART_H
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#include "gd32f4xx.h"
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/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */
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#define USART1 USART_BASE /*!< USART1 base address */
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#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */
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#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */
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#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */
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#define UART6 (USART_BASE+0x00003400U) /*!< UART6 base address */
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#define UART7 (USART_BASE+0x00003800U) /*!< UART7 base address */
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#define USART0 (USART_BASE+0x0000CC00U) /*!< USART0 base address */
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#define USART5 (USART_BASE+0x0000D000U) /*!< USART5 base address */
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/* registers definitions */
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#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */
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#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */
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#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */
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#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */
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#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */
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#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */
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#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */
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#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */
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#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */
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#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */
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#define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */
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/* bits definitions */
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/* USARTx_STAT0 */
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#define USART_STAT0_PERR BIT(0) /*!< parity error flag */
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#define USART_STAT0_FERR BIT(1) /*!< frame error flag */
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#define USART_STAT0_NERR BIT(2) /*!< noise error flag */
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#define USART_STAT0_ORERR BIT(3) /*!< overrun error */
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#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */
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#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */
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#define USART_STAT0_TC BIT(6) /*!< transmission complete */
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#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */
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#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */
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#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */
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/* USARTx_DATA */
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#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */
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/* USARTx_BAUD */
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#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */
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#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */
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/* USARTx_CTL0 */
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#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
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#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
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#define USART_CTL0_REN BIT(2) /*!< receiver enable */
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#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */
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#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
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#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
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#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
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#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */
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#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
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#define USART_CTL0_PM BIT(9) /*!< parity mode */
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#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */
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#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
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#define USART_CTL0_WL BIT(12) /*!< word length */
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#define USART_CTL0_UEN BIT(13) /*!< USART enable */
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#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
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/* USARTx_CTL1 */
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#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
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#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
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#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */
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#define USART_CTL1_CLEN BIT(8) /*!< CK length */
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#define USART_CTL1_CPH BIT(9) /*!< CK phase */
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#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
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#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */
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#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
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#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */
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/* USARTx_CTL2 */
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#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */
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#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */
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#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
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#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
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#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
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#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
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#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */
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#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */
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#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */
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#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */
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#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
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#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */
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/* USARTx_GP */
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#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
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#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
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/* USARTx_CTL3 */
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#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */
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#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */
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#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */
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#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */
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#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */
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#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */
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#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */
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#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */
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/* USARTx_RT */
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#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */
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#define USART_RT_BL BITS(24,31) /*!< block length */
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/* USARTx_STAT1 */
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#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */
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#define USART_STAT1_EBF BIT(12) /*!< end of block flag */
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#define USART_STAT1_BSY BIT(16) /*!< busy flag */
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/* USARTx_CHC */
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#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */
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#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */
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#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */
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#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */
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/* constants definitions */
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/* define the USART bit position and its register index offset */
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#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
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#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
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#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
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| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
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#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
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#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
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/* register offset */
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#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */
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#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */
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#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */
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#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */
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#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */
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#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */
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#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */
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/* USART flags */
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typedef enum
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{
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/* flags in STAT0 register */
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USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */
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USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */
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USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */
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USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */
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USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */
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USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
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USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */
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USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */
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USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */
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USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */
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/* flags in STAT1 register */
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USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */
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USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */
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USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */
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/* flags in CHC register */
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USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */
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}usart_flag_enum;
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/* USART interrupt flags */
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typedef enum
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{
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/* interrupt flags in CTL0 register */
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USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
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USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
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USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
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USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
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USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
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USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
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/* interrupt flags in CTL1 register */
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USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
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/* interrupt flags in CTL2 register */
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USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
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USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
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USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
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USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
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/* interrupt flags in CTL3 register */
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USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */
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USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */
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}usart_interrupt_flag_enum;
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/* USART interrupt flags */
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typedef enum
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{
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/* interrupt in CTL0 register */
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USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
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USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
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USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
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USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
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USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
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/* interrupt in CTL1 register */
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USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
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/* interrupt in CTL2 register */
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USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
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USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
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/* interrupt in CTL3 register */
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USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */
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USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */
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}usart_interrupt_enum;
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/* USART invert configure */
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typedef enum
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{
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/* data bit level inversion */
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USART_DINV_ENABLE, /*!< data bit level inversion */
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USART_DINV_DISABLE, /*!< data bit level not inversion */
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/* TX pin level inversion */
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USART_TXPIN_ENABLE, /*!< TX pin level inversion */
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USART_TXPIN_DISABLE, /*!< TX pin level not inversion */
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/* RX pin level inversion */
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USART_RXPIN_ENABLE, /*!< RX pin level inversion */
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USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
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}usart_invert_enum;
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/* USART receiver configure */
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#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
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#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
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#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
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/* USART transmitter configure */
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#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
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#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
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#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
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/* USART parity bits definitions */
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#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
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#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
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#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
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#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
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/* USART wakeup method in mute mode */
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#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
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#define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */
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#define USART_WM_ADDR CTL0_WM(1) /*!< address mask */
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/* USART word length definitions */
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#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
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#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
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#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
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/* USART oversampling mode definitions */
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#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
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#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */
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#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */
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/* USART stop bits definitions */
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#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
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#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
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#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
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#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
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#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
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/* USART LIN break frame length */
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#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
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#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */
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#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */
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/* USART CK length */
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#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
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#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
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#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
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/* USART clock phase */
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#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
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#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
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#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
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/* USART clock polarity */
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#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
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#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
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#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
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/* USART DMA request for receive configure */
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#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
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#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */
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#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */
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/* USART DMA request for transmission configure */
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#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
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#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */
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#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */
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/* USART RTS configure */
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#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
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#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */
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#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */
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/* USART CTS configure */
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#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
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#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */
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#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */
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/* USART one sample bit method configure */
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#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
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#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */
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#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */
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/* USART IrDA low-power enable */
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#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
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#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
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#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
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/* USART data is transmitted/received with the LSB/MSB first */
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#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11))
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#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */
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#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */
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/* break frame coherence mode */
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#define CHC_BCM(regval) (BIT(2) & ((uint32_t)(regval) << 2))
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#define USART_BCM_NONE CHC_BCM(0) /*!< no parity error is detected */
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#define USART_BCM_EN CHC_BCM(1) /*!< parity error is detected */
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/* USART parity check coherence mode */
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#define CHC_PCM(regval) (BIT(1) & ((uint32_t)(regval) << 1))
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#define USART_PCM_NONE CHC_PCM(0) /*!< not check parity */
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#define USART_PCM_EN CHC_PCM(1) /*!< check the parity */
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/* USART hardware flow control coherence mode */
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#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0))
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#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */
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#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */
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/* function declarations */
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/* initialization functions */
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/* reset USART */
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void usart_deinit(uint32_t usart_periph);
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/* configure usart baud rate value */
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void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
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/* configure usart parity function */
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void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
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/* configure usart word length */
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void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
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/* configure usart stop bit length */
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void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
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/* enable usart */
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void usart_enable(uint32_t usart_periph);
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/* disable usart */
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void usart_disable(uint32_t usart_periph);
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/* configure USART transmitter */
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void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
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/* configure USART receiver */
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void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
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/* USART normal mode communication */
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/* data is transmitted/received with the LSB/MSB first */
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void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
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/* configure USART inverted */
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void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
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/* configure the USART oversample mode */
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void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
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/* configure sample bit method */
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void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm);
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/* enable receiver timeout */
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void usart_receiver_timeout_enable(uint32_t usart_periph);
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/* disable receiver timeout */
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void usart_receiver_timeout_disable(uint32_t usart_periph);
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/* configure receiver timeout threshold */
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void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
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/* USART transmit data function */
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void usart_data_transmit(uint32_t usart_periph, uint32_t data);
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/* USART receive data function */
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uint16_t usart_data_receive(uint32_t usart_periph);
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/* multi-processor communication */
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/* configure address of the USART */
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void usart_address_config(uint32_t usart_periph, uint8_t addr);
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/* enable mute mode */
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void usart_mute_mode_enable(uint32_t usart_periph);
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/* disable mute mode */
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void usart_mute_mode_disable(uint32_t usart_periph);
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/* configure wakeup method in mute mode */
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void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod);
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/* LIN mode communication */
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/* enable LIN mode */
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void usart_lin_mode_enable(uint32_t usart_periph);
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/* disable LIN mode */
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void usart_lin_mode_disable(uint32_t usart_periph);
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/* LIN break detection length */
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void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
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/* send break frame */
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void usart_send_break(uint32_t usart_periph);
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/* half-duplex communication */
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/* enable half-duplex mode */
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void usart_halfduplex_enable(uint32_t usart_periph);
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/* disable half-duplex mode */
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void usart_halfduplex_disable(uint32_t usart_periph);
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/* synchronous communication */
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/* enable CK pin in synchronous mode */
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void usart_synchronous_clock_enable(uint32_t usart_periph);
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/* disable CK pin in synchronous mode */
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void usart_synchronous_clock_disable(uint32_t usart_periph);
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/* configure usart synchronous mode parameters */
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void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
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/* smartcard communication */
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/* configure guard time value in smartcard mode */
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void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
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/* enable smartcard mode */
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void usart_smartcard_mode_enable(uint32_t usart_periph);
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/* disable smartcard mode */
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void usart_smartcard_mode_disable(uint32_t usart_periph);
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/* enable NACK in smartcard mode */
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void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
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/* disable NACK in smartcard mode */
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void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
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/* configure smartcard auto-retry number */
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void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
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/* configure block length */
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void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
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/* IrDA communication */
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/* enable IrDA mode */
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void usart_irda_mode_enable(uint32_t usart_periph);
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/* disable IrDA mode */
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void usart_irda_mode_disable(uint32_t usart_periph);
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/* configure the peripheral clock prescaler */
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void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
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/* configure IrDA low-power */
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void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
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/* hardware flow communication */
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/* configure hardware flow control RTS */
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void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
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/* configure hardware flow control CTS */
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void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
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/* coherence control */
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/* configure break frame coherence mode */
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void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm);
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/* configure parity check coherence mode */
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void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm);
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/* configure hardware flow control coherence mode */
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void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm);
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/* DMA communication */
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/* configure USART DMA for reception */
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void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
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/* configure USART DMA for transmission */
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void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
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/* flag & interrupt functions */
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/* get flag in STAT0/STAT1 register */
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FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
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/* clear flag in STAT0/STAT1 register */
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void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
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/* enable USART interrupt */
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void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt);
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/* disable USART interrupt */
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void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt);
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/* get USART interrupt and flag status */
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FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
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/* clear interrupt flag in STAT0/STAT1 register */
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void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
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#endif /* GD32F4XX_USART_H */
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