9a27de92ae
This patch optimizes the user-space context handling in the ARM64 architecture, specifically improving how the context is saved and restored during system calls and interrupts. The changes make the code more efficient and easier to maintain, while ensuring proper preservation of user context during system transitions. Changes: - Introduced a parameter for context saving to improve flexibility. - Replaced hardcoded stack pointer operations with frame-relative references for better readability and code reuse. - Simplified context restoration, removing redundant operations like loading/storing floating-point registers. Signed-off-by: Shell <smokewood@qq.com>
129 lines
3.0 KiB
C
129 lines
3.0 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-03-28 Shell Move vector handling codes from context_gcc.S
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* 2024-04-08 Shell Optimizing exception switch between u-space/kernel,
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*/
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#ifndef __ARM64_INC_VECTOR_H__
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#define __ARM64_INC_VECTOR_H__
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#include "asm-generic.h"
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#include <rtconfig.h>
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#include <asm-fpu.h>
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#include <armv8.h>
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.macro SAVE_IRQ_CONTEXT
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/* Save the entire context. */
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SAVE_FPU sp
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stp x0, x1, [sp, #-0x10]!
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stp x2, x3, [sp, #-0x10]!
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stp x4, x5, [sp, #-0x10]!
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stp x6, x7, [sp, #-0x10]!
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stp x8, x9, [sp, #-0x10]!
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stp x10, x11, [sp, #-0x10]!
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stp x12, x13, [sp, #-0x10]!
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stp x14, x15, [sp, #-0x10]!
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stp x16, x17, [sp, #-0x10]!
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stp x18, x19, [sp, #-0x10]!
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stp x20, x21, [sp, #-0x10]!
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stp x22, x23, [sp, #-0x10]!
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stp x24, x25, [sp, #-0x10]!
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stp x26, x27, [sp, #-0x10]!
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stp x28, x29, [sp, #-0x10]!
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mrs x28, fpcr
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mrs x29, fpsr
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stp x28, x29, [sp, #-0x10]!
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mrs x29, sp_el0
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stp x29, x30, [sp, #-0x10]!
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mrs x3, spsr_el1
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mrs x2, elr_el1
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stp x2, x3, [sp, #-0x10]!
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.endm
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#ifdef RT_USING_SMP
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#include "../mp/context_gcc.h"
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#else
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#include "../up/context_gcc.h"
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#endif
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.macro RESTORE_IRQ_CONTEXT_NO_SPEL0
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ldp x2, x3, [sp], #0x10
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msr elr_el1, x2
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msr spsr_el1, x3
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ldp x29, x30, [sp], #0x10
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ldp x28, x29, [sp], #0x10
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msr fpcr, x28
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msr fpsr, x29
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ldp x28, x29, [sp], #0x10
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ldp x26, x27, [sp], #0x10
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ldp x24, x25, [sp], #0x10
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ldp x22, x23, [sp], #0x10
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ldp x20, x21, [sp], #0x10
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ldp x18, x19, [sp], #0x10
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ldp x16, x17, [sp], #0x10
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ldp x14, x15, [sp], #0x10
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ldp x12, x13, [sp], #0x10
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ldp x10, x11, [sp], #0x10
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ldp x8, x9, [sp], #0x10
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ldp x6, x7, [sp], #0x10
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ldp x4, x5, [sp], #0x10
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ldp x2, x3, [sp], #0x10
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ldp x0, x1, [sp], #0x10
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RESTORE_FPU sp
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.endm
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.macro EXCEPTION_SWITCH, eframex, tmpx
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#ifdef RT_USING_SMART
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/**
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* test the spsr for execution level 0
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* That is { PSTATE.[NZCV] := SPSR_EL1 & M.EL0t }
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*/
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ldr \tmpx, [\eframex, #CONTEXT_OFFSET_SPSR_EL1]
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and \tmpx, \tmpx, 0x1f
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cbz \tmpx, 1f
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b 2f
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1:
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b arch_ret_to_user
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2:
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#endif /* RT_USING_SMART */
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.endm
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.macro SAVE_USER_CTX, eframex, tmpx
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#ifdef RT_USING_SMART
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mrs \tmpx, spsr_el1
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and \tmpx, \tmpx, 0xf
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cbz \tmpx, 1f
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b 2f
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1:
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mov x0, \eframex
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bl lwp_uthread_ctx_save
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2:
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#endif /* RT_USING_SMART */
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.endm
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.macro RESTORE_USER_CTX, eframex, tmpx
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#ifdef RT_USING_SMART
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ldr \tmpx, [\eframex, #CONTEXT_OFFSET_SPSR_EL1]
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and \tmpx, \tmpx, 0x1f
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cbz \tmpx, 1f
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b 2f
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1:
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bl lwp_uthread_ctx_restore
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2:
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#endif /* RT_USING_SMART */
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.endm
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#endif /* __ARM64_INC_VECTOR_H__ */
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