181 lines
4.9 KiB
C
181 lines
4.9 KiB
C
/*
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* @ : Copyright (c) 2021 Phytium Information Technology, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0.
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*
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* Date: 2021-03-30 14:57:03
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* @LastEditTime: 2021-05-24 14:35:00
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* Description: definitions of BSP parameters
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* Modify History:
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* * * Ver Who Date Changes
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* * ----- ------ -------- ----------------------------------------------
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* 1.00 Huanghe 2021/3/1 init
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*/
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#ifndef FT_PARAMETERS_H
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#define FT_PARAMETERS_H
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/* Device register address */
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#define FT_DEV_BASE_ADDR 0x28000000
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#define FT_DEV_END_ADDR 0x2FFFFFFF
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/******** UART ************/
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#define FT_UART_NUM 4
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#define FT_UART_REG_LENGTH 0x18000
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#define FT_UART0_ID 0
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#define FT_UART0_BASE_ADDR 0x28000000
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#define FT_UART0_CLK_FREQ_HZ 48000000
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#define FT_UART1_ID 1
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#define FT_UART1_BASE_ADDR 0x28001000
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#define FT_UART1_CLK_FREQ_HZ 48000000
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#define FT_UART2_ID 2
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#define FT_UART2_BASE_ADDR 0x28002000
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#define FT_UART2_CLK_FREQ_HZ 48000000
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#define FT_UART3_BASE_ADDR 0x28003000
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#define FT_UART3_ID 3
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#define FT_UART3_CLK_FREQ_HZ 48000000
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#define FT_STDOUT_BASEADDRESS FT_UART1_BASE_ADDR
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#define FT_STDIN_BASEADDRESS FT_UART1_BASE_ADDR
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/****** GIC v3 *****/
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#define FT_GICV3_INSTANCES_NUM 1U
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#define GICV3_REG_LENGTH 0x00009000
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/*
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* The maximum priority value that can be used in the GIC.
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*/
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#define GICV3_MAX_INTR_PRIO_VAL 240U
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#define GICV3_INTR_PRIO_MASK 0x000000f0U
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#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
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#define SGI_INT_MAX 16
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#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
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#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
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#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
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#define FT_GICV3_BASEADDRESS 0x29900000U
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#define FT_GICV3_DISTRIBUTOR_BASEADDRESS (FT_GICV3_BASEADDRESS + 0)
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#define FT_GICV3_RD_BASEADDRESS (FT_GICV3_BASEADDRESS + 0x80000U)
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#define FT_GICV3_SGI_BASEADDRESS (FT_GICV3_RD_BASEADDRESS + (1U << 16))
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#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
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/** Gmac **/
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#define FT_GMAC_INSTANCES_NUM 2U
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#define FT_GMAC_REG_LENGTH 0x00009000
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#define FT_GMAC_COMMON_ADDR 0x2820B000U
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#define FT_GMAC0_ID 0
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#define FT_GMAC0_BASEADDR 0x2820C000U
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#define FT_GMAC0_DEFAULT_ADDR \
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{ \
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0x11, 0x1c, 0x2c, 0x5c, 0x66, 0x88 \
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}
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#define FT_GMAC1_ID 1
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#define FT_GMAC1_BASEADDR 0x28210000U
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/** @defgroup ENET_Buffers_setting
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* @{
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*/
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#define GMAC_MAX_PACKET_SIZE 1600 /* GMAC_HEADER + GMAC_EXTRA + VLAN_TAG + MAX_GMAC_PAYLOAD + GMAC_CRC */
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#define GMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
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#define GMAC_CRC 4 /* Gmac CRC */
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#define GMAC_EXTRA 2 /* Extra bytes in some cases */
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#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
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#define MIN_GMAC_PAYLOAD 46 /* Minimum Gmac payload size */
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#define MAX_GMAC_PAYLOAD 1500 /* Maximum Gmac payload size */
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#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
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#define RX_DESCNUM 1024U /* Rx buffers of size GMAC_MAX_PACKET_SIZE */
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#define TX_DESCNUM 1024U /* Tx buffers of size GMAC_MAX_PACKET_SIZE */
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#define PHY_USING_AR8035
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#define GMAC0_ISRNUM 81
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#define GMAC0_ISRPRIORITY 0
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#define GMAC1_ISRNUM 82
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#define GMAC1_ISRPRIORITY 0
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/* SDC */
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#define FT_SDC_NUM 1
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#define FT_SDC_INSTANCE 0
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#define FT_SDC_BASEADDR 0x28207C00U
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#define FT_SDC_REG_LENGTH 0x4000
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#define FT_SDC_FREQ 600000000
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/* pin MUX/DEMUX */
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#define FT_PIN_MUX_BASEADDR 0x28180000
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#define FT_PIN_MUX_REG_LENGTH 0x10000
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/* CAN */
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#define FT_CAN_NUM 3
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#define FT_CAN_REG_LENGTH 0x1000
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#define FT_CAN0_BASEADDR 0x28207000
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#define FT_CAN1_BASEADDR 0x28207400
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#define FT_CAN2_BASEADDR 0x28207800
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#define FT_CAN0_IRQNUM 119
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#define FT_CAN1_IRQNUM 123
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#define FT_CAN2_IRQNUM 124
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#define FT_CAN_BAUDRATE 1000000 /* 1M */
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#define FT_CAN_CLK 600000000
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/* pci */
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#define FT_PCI_CONFIG_BASEADDR 0x40000000
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#define FT_PCI_CONFIG_REG_LENGTH 0x10000000
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#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000
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#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000
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#define FT_PCI_MEM32_BASEADDR 0x58000000
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#define FT_PCI_MEM32_REG_LENGTH 0x27000000
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/* qspi */
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#define FT_QSPI_NUM 1U
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#define FT_QSPI_INSTANCE 0
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#define FT_QSPI_MAX_CS_NUM 4
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#define FT_QSPI_BASEADDR 0x28014000
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#define FT_QSPI_FLASH_CAP_4MB 0
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#define FT_QSPI_FLASH_CAP_8MB 1
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#define FT_QSPI_FLASH_CAP_16MB 2
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#define FT_QSPI_FLASH_CAP_32MB 3
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#define FT_QSPI_FLASH_CAP_64MB 4
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#define FT_QSPI_FLASH_CAP_128MB 5
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#define FT_QSPI_FLASH_CAP_256MB 6
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#define FT_QSPI_ADDR_SEL_3 0
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#define FT_QSPI_ADDR_SEL_4 1
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#define FT_QSPI_SCK_DIV_128 0
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#define FT_QSPI_SCK_DIV_2 1
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#define FT_QSPI_SCK_DIV_4 2
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#define FT_QSPI_SCK_DIV_8 3
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#define FT_QSPI_SCK_DIV_16 4
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#define FT_QSPI_SCK_DIV_32 5
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#define FT_QSPI_SCK_DIV_64 6
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#define FT_QSPI_TRANSFER_1_1_1 0
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#define FT_QSPI_TRANSFER_1_1_2 1
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#define FT_QSPI_TRANSFER_1_1_4 2
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#define FT_QSPI_TRANSFER_1_2_2 3
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#define FT_QSPI_TRANSFER_1_4_4 4
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#define FT_QSPI_TRANSFER_2_2_2 5
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#define FT_QSPI_TRANSFER_4_4_4 6
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/* smp */
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#define FT_SMP_EN
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#endif // !
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