323 lines
9.8 KiB
C
323 lines
9.8 KiB
C
/** @file dma.c
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* @brief DMA Driver Inmplmentation File
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* @date 29.May.2013
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* @version 03.05.02
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*
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#include "sys_dma.h"
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/** @fn void dmaEnable(void)
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* @brief enables DMA module
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*
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* This function brings DMA out of reset
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*/
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void dmaEnable(void)
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{
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dmaREG->GCTRL = 0x00000001U; /* reset dma */
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dmaREG->GCTRL |= 0x00010000U; /* enable dma */
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dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */
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}
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/** @fn void dmaDisable(void)
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* @brief disables DMA module
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*
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* This function disables DMA module
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*/
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void dmaDisable(void)
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{
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/* Wait until DMA's external bus has completed data transfer */
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while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U)
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{
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} /* Wait */
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/* Disable DMA module */
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dmaREG->GCTRL = 0U;
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}
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/** @fn void dmaReqAssign(uint32 channel,uint32 reqline)
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* @brief Initializes the DMA Driver
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* @param[in] channel DMA channel
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* @param[in] reqline DMA request line
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*
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* This function assigns dma request lines to channels
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*/
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void dmaReqAssign(uint32 channel,uint32 reqline)
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{
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register uint32 i=0U,j=0U;
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i = channel >> 2U; /* Find the register to configure */
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j = channel -(i<<2U); /* Find the offset of the type */
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j = 3U-j; /* reverse the byte order */
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j = j<<3U; /* find the bit location */
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/* mapping channel 'i' to request line 'j' */
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dmaREG->DREQASI[i] &= ~(0xffU<<j);
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dmaREG->DREQASI[i] |= (reqline<<j);
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}
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/** @fn uint32 dmaGetReq(uint32 channel)
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* @brief Gets the request line number mapped to the selected channel
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* @param[in] channel DMA channel
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*
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* This function returns the request line number mapped to the selected channel
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*/
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uint32 dmaGetReq(uint32 channel)
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{
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register uint32 i=0U,j=0U;
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i = channel >> 2U; /* Find the register to configure */
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j = channel -(i<<2U); /* Find the offset of the type */
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j = 3U-j; /* reverse the byte order */
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j = j<<3U; /* find the bit location */
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return ((dmaREG->DREQASI[i] >> j) &0xffU);
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}
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/** @fn void dmaSetCtrlPacket(uint32 channel)
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* @brief Initializes the DMA Driver
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*
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* This function sets control packet
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*/
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void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT)
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{
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register uint32 i=0U,j=0U;
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dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD;
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dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD;
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dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT;
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dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14U) | (g_dmaCTRLPKT.WRSIZE << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \
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(g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT);
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dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U);
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dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET);
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dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET);
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i = channel >> 3U; /* Find the register to write */
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j = channel -(i << 3U); /* Find the offset of the 4th bit */
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j = 7U -j; /* Reverse the order of the 4th bit offset */
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j = j<<2U; /* Find the bit location of the 4th bit to write */
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dmaREG->PAR[i] &= ~(0xfU<<j);
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dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);
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}
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/** @fn void dmaSetChEnable(uint32 channel,uint32 type)
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* @brief Enable channel
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* @param[in] channel DMA channel
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* @param[in] type Type of triggering
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* - DMA_HW: Enables the selected DMA channel for hardware triggering
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* - DMA_SW: Enables the selected DMA channel for software triggering
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*
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* This function enables the DMA channel for hardware or software triggering
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*/
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void dmaSetChEnable(uint32 channel,uint32 type)
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{
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if(type == DMA_HW)
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{
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dmaREG->HWCHENAS = (1U << channel);
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}
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else if(type == DMA_SW)
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{
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dmaREG->SWCHENAS = (1U << channel);
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}
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else
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{
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/** Empty */
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}
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}
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/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
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* @brief Assign Priority to the channel
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* @param[in] channel DMA channel
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* @param[in] priority Priority queue to which channel needs to be assigned
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* - LOWPRIORITY : The selected channel will be assigned to low priority queue
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* - HIGHPRIORITY: The selected channel will be assigned to high priority queue
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*
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* This function assigns the selected priority to the selected channel
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*/
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void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
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{
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if (priority == LOWPRIORITY)
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{
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dmaREG->CHPRIOR |= 1U << channel;
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}
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else
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{
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dmaREG->CHPRIOS |= 1U << channel;
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}
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}
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/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
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* @brief Enable selected interrupt
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* @param[in] channel DMA channel
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* @param[in] inttype Interrupt to be enabled
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* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
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* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
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* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
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* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
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* - BER: Bus Error Interrupt will be disabled for the selected channel
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*
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* This function enables the selected interrupt for the selected channel
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*/
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void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
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{
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dmaREG->GCHIENAS = 1 << channel;
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switch (inttype)
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{
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case FTC: dmaREG->FTCINTENAS |= 1U << channel;
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break;
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case LFS: dmaREG->LFSINTENAS |= 1U << channel;
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break;
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case HBC: dmaREG->HBCINTENAS |= 1U << channel;
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break;
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case BTC: dmaREG->BTCINTENAS |= 1U << channel;
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break;
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default :
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break;
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}
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}
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/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
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* @brief Disable selected interrupt
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* @param[in] channel DMA channel
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* @param[in] inttype Interrupt to be disabled
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* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
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* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
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* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
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* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
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* - BER: Bus Error Interrupt will be disabled for the selected channel
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*
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* This function disables the selected interrupt for the selected channel
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*/
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void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
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{
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switch (inttype)
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{
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case FTC: dmaREG->FTCINTENAR |= 1U << channel;
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break;
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case LFS: dmaREG->LFSINTENAR |= 1U << channel;
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break;
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case HBC: dmaREG->HBCINTENAR |= 1U << channel;
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break;
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case BTC: dmaREG->BTCINTENAR |= 1U << channel;
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break;
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default :
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break;
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}
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}
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/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
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* @brief Configure start and end address of the region
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* @param[in] region Memory Region
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* - DMA_REGION0
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* - DMA_REGION1
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* - DMA_REGION2
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* - DMA_REGION3
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* @param[in] start_add Start address of the the region
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* @param[in] end_add End address of the region
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*
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* This function configure start and end address of the selected region
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*/
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void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
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{
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dmaREG->DMAMPR[region].STARTADD = start_add;
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dmaREG->DMAMPR[region].ENDADD = end_add;
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}
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/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
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* @brief Enable the selected region
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* @param[in] region Memory Region
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* - DMA_REGION0
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* - DMA_REGION1
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* - DMA_REGION2
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* - DMA_REGION3
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* @param[in] access Access permission of the selected region
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* - FULLACCESS
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* - READONLY
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* - WRITEONLY
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* - NOACCESS
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* @param[in] intenable Interrupt to be enabled or not
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* - INTERRUPT_ENABLE : Enable interrupt for the selected region
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* - INTERRUPT_DISABLE: Disable interrupt for the selected region
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*
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* This function enables the selected region with selected access permission with or without interrupt enable
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*/
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void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
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{
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/* Enable the region */
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dmaREG->DMAMPCTRL |= 1U << (region*8U);
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/* Set access permission for the region */
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dmaREG->DMAMPCTRL |= access << ((region*8U) + 1U);
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/* Enable or Disable interrupt */
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dmaREG->DMAMPCTRL |= intenable << ((region*8U) + 3U);
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}
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/** @fn void dmaDisableRegion(dmaREGION_t region)
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* @brief Disable the selected region
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* @param[in] region Memory Region
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* - DMA_REGION0
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* - DMA_REGION1
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* - DMA_REGION2
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* - DMA_REGION3
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*
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* This function disables the selected region(no address checking done).
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*/
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void dmaDisableRegion(dmaREGION_t region)
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{
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dmaREG->DMAMPCTRL &= ~(1U << (region*8U));
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}
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/** @fn void dmaEnableParityCheck(void)
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* @brief Enable Parity Check
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*
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* This function enables parit check
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*/
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void dmaEnableParityCheck(void)
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{
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dmaREG->DMAPCR = 0x5U;
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}
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/** @fn void dmaDisableParityCheck(void)
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* @brief Disable Parity Check
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*
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* This function disables parity check
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*/
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void dmaDisableParityCheck(void)
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{
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dmaREG->DMAPCR = 0xAU;
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}
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