588 lines
18 KiB
C
588 lines
18 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-09-24 qiyu first version
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*/
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#include "rtdbg.h"
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#include "drv_pwm.h"
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#include "F2837xD_device.h"
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#include "F28x_Project.h" /* Device Headerfile and Examples Include File */
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#include "drv_config.h"
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#include "F2837xD_epwm.h"
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/*
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* for now, cpu rate is a fixed value, waiting to be modified to an auto-ajustable variable.
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*/
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#ifdef BSP_USING_PWM
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rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data);
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#define CPU_FREQUENCY 200e6
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/*
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* TODO unknown issue, according to the configuration,
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* this division should be 2,
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* while 2 is inconsistent with the measured result
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*/
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#define PWM_DIVISION 2
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#define CHANNEL_A 1
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#define CHANNEL_B 2
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#define UPDOWN 1
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enum
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{
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#ifdef BSP_USING_PWM1
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PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_INDEX,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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PWM8_INDEX,
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#endif
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#ifdef BSP_USING_PWM9
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PWM9_INDEX,
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#endif
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#ifdef BSP_USING_PWM10
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PWM10_INDEX,
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#endif
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#ifdef BSP_USING_PWM11
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PWM11_INDEX,
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#endif
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#ifdef BSP_USING_PWM12
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PWM12_INDEX,
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#endif
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};
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops rt_pwm_ops =
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{
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drv_pwm_control
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};
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static struct c28x_pwm c28x_pwm_obj[] =
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{
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#ifdef BSP_USING_PWM1
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PWM1_CONFIG,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_CONFIG,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_CONFIG,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_CONFIG,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_CONFIG,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_CONFIG,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_CONFIG,
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#endif
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#ifdef BSP_USING_PWM8
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PWM8_CONFIG,
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#endif
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};
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static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_configuration *configuration)
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{
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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/*
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* TODO Unknown problem
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* the clock division configuration of PWM module is 1
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* however, the experiment result shows the division is 2
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*/
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/* Set the configuration of PWM according to the parameter*/
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rt_uint32_t prd = configuration->period/(1e9/(CPU_FREQUENCY/PWM_DIVISION))/2;
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rt_uint32_t comp = prd*configuration->pulse/configuration->period;
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rt_uint32_t dead_time = configuration->dead_time/(1e9/(CPU_FREQUENCY/PWM_DIVISION));
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rt_uint32_t phase = configuration->phase;
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epwm->TBPRD = prd; /* Set timer period*/
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epwm->TBCTR = 0x0000; /* Clear counter*/
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epwm->CMPCTL.bit.SHDWAMODE = RT_SHADOW_MODE; /* Load registers every ZERO*/
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epwm->CMPCTL.bit.SHDWBMODE = RT_SHADOW_MODE;
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/* Setup compare */
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if(configuration->channel == CHANNEL_A)
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{
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epwm->CMPA.bit.CMPA = comp;
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}else
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{
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epwm->CMPB.bit.CMPB = comp;
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}
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/* Set actions */
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epwm->AQCTLA.bit.CAU = AQ_CLEAR; /* Set PWMA on Zero*/
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epwm->AQCTLA.bit.CAD = AQ_SET;
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epwm->AQCTLB.bit.CBU = AQ_CLEAR; /* Set PWMB on Zero*/
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epwm->AQCTLB.bit.CBD = AQ_SET;
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/* Active Low PWMs - Setup Deadband */
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/* TODO finish complementary setting */
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epwm->DBCTL.bit.POLSEL = DB_ACTV_HIC;
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epwm->DBRED.bit.DBRED = dead_time;
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epwm->DBFED.bit.DBFED = dead_time;
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epwm->DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
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/*
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if(configuration->complementary)
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{
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}
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else
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{
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epwm->DBRED.bit.DBRED = 0;
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epwm->DBFED.bit.DBFED = 0;
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epwm->DBCTL.bit.POLSEL = DB_ACTV_HI;
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epwm->DBCTL.bit.OUT_MODE = DB_DISABLE;
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}
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*/
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epwm->DBCTL.bit.IN_MODE = DBA_ALL;
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/* if disable dead time, set dead_time to 0 */
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#ifdef BSP_PWM1_CTR_MODE_UPDOWN
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if(phase<180)
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{
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epwm->TBPHS.bit.TBPHS = prd * phase/180;
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epwm->TBCTL.bit.PHSDIR = 0; /* count up */
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}else
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{
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epwm->TBPHS.bit.TBPHS = prd-prd * (phase-180)/180;
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epwm->TBCTL.bit.PHSDIR = 1; /* count up*/
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}
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#endif
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if(epwm == &EPwm1Regs)
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{
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epwm->TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
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epwm->TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
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}else
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{
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epwm->TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
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epwm->TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(struct EPWM_REGS *epwm,struct rt_pwm_configuration *configuration)
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{
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/* Retrieve the pwm configuration */
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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rt_uint32_t prd = epwm->TBPRD;
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rt_uint32_t comp = epwm->CMPA.bit.CMPA;
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if(UPDOWN)
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{
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/* if in updown mode, period in configuration has to be doubled */
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configuration->period = prd*(1e9/(CPU_FREQUENCY/PWM_DIVISION))*2;
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}
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else
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{
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configuration->period = prd*(1e9/(CPU_FREQUENCY/PWM_DIVISION));
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}
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configuration->pulse = comp*configuration->period/prd;
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_period(struct EPWM_REGS *epwm, rt_uint32_t period)
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{
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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rt_uint32_t prd = period/(1e9/(CPU_FREQUENCY/PWM_DIVISION))/2;
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epwm->TBPRD = prd; /* Set timer period */
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_pulse(struct EPWM_REGS *epwm, int channel, rt_uint32_t pulse)
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{
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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rt_uint32_t comp = pulse/(1e9/(CPU_FREQUENCY/PWM_DIVISION));
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if(channel == CHANNEL_A)
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{
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epwm->CMPA.bit.CMPA = comp; /* set comparator value */
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}else
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{
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epwm->CMPB.bit.CMPB = comp; /* set comparator value */
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_dead_time(struct EPWM_REGS *epwm, rt_uint32_t dead_time)
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{
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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rt_uint32_t _dead_time = dead_time/(1e9/(CPU_FREQUENCY/PWM_DIVISION));
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epwm->DBRED.bit.DBRED = _dead_time; /* rising dead time */
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epwm->DBFED.bit.DBFED = _dead_time; /* falling dead time */
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set_phase(struct EPWM_REGS *epwm, rt_uint32_t phase)
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{
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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if(phase<180)
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{
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epwm->TBPHS.bit.TBPHS = epwm->TBPRD * phase/180;
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epwm->TBCTL.bit.PHSDIR = 0;/* count up */
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}else
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{
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epwm->TBPHS.bit.TBPHS = epwm->TBPRD-epwm->TBPRD * (phase-180)/180;
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epwm->TBCTL.bit.PHSDIR = 1;/* count up */
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_enable_irq(volatile struct EPWM_REGS *epwm,rt_bool_t enable)
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{
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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if(enable == RT_TRUE)
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{
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/* Interrupt setting */
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epwm->ETSEL.bit.INTEN = 1; /* Enable INT */
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}else{
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epwm->ETSEL.bit.INTEN = 0; /* Enable INT */
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_enable(volatile struct EPWM_REGS *epwm,rt_bool_t enable)
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{
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/*
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* TODO
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* Still not sure about how to stop PWM in C2000
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*/
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if(epwm == RT_NULL)
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{
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return -RT_ERROR;
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}
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if(enable == RT_TRUE)
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{
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/* clear trip zone flag */
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EALLOW;
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epwm->TZCLR.bit.OST = 1;
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EDIS;
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}
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else
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{
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/* set trip zone flag */
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EALLOW;
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epwm->TZFRC.bit.OST = 1;
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EDIS;
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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struct c28x_pwm *pwm = (struct c28x_pwm *)device->parent.user_data;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return drv_pwm_enable((struct EPWM_REGS *)(pwm->pwm_regs), RT_TRUE);
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case PWM_CMD_DISABLE:
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return drv_pwm_enable((struct EPWM_REGS *)(pwm->pwm_regs), RT_FALSE);
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case PWM_CMD_SET:
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return drv_pwm_set((struct EPWM_REGS *)(pwm->pwm_regs), configuration);
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case PWM_CMD_GET:
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return drv_pwm_get((struct EPWM_REGS *)(pwm->pwm_regs), configuration);
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case PWM_CMD_SET_PERIOD:
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return drv_pwm_set_period((struct EPWM_REGS *)(pwm->pwm_regs), configuration->period);
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case PWM_CMD_SET_PULSE:
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return drv_pwm_set_pulse((struct EPWM_REGS *)(pwm->pwm_regs), configuration->channel,configuration->pulse);
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case PWM_CMD_SET_DEAD_TIME:
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return drv_pwm_set_dead_time((struct EPWM_REGS *)(pwm->pwm_regs), configuration->dead_time);
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case PWM_CMD_SET_PHASE:
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return drv_pwm_set_phase((struct EPWM_REGS *)(pwm->pwm_regs), configuration->phase);
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case PWM_CMD_ENABLE_IRQ:
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return drv_pwm_enable_irq((struct EPWM_REGS *)(pwm->pwm_regs), RT_TRUE);
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case PWM_CMD_DISABLE_IRQ:
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return drv_pwm_enable_irq((struct EPWM_REGS *)(pwm->pwm_regs), RT_FALSE);
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default:
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return RT_EINVAL;
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}
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}
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static void pwm_isr(struct rt_device_pwm *rt_pwm)
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{
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struct c28x_pwm *pwm;
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pwm = (struct c28x_pwm *)rt_pwm->parent.user_data;
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
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pwm->pwm_regs->ETCLR.bit.INT = 1;
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}
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#define EPWM_ISR_DEFINE(i) void EPWM##i##_Isr(){\
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rt_interrupt_enter(); \
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pwm_isr(&(c28x_pwm_obj[PWM##i##_INDEX].pwm_device)); \
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rt_interrupt_leave(); \
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}
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#ifdef BSP_PWM1_IT_ENABLE
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EPWM_ISR_DEFINE(1)
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void EPWM1_Isr();
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#endif
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#ifdef BSP_PWM2_IT_ENABLE
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EPWM_ISR_DEFINE(2)
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void EPWM2_Isr();
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#endif
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#ifdef BSP_PWM3_IT_ENABLE
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EPWM_ISR_DEFINE(3)
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void EPWM3_Isr();
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#endif
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#ifdef BSP_PWM4_IT_ENABLE
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EPWM_ISR_DEFINE(4)
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void EPWM4_Isr();
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#endif
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static int c28x_hw_pwm_init(struct c28x_pwm *device)
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{
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IER |= M_INT3;
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rt_err_t result = 0;
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EALLOW;
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#ifdef BSP_USING_PWM1
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GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4; /* Disable pull-up(EPWM1A) */
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GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4; /* Configure as EPWM1A */
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EPwm1Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
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EPwm1Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
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EPwm1Regs.TBCTL.bit.CTRMODE = BSP_PWM1_CTRMODE;
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM1_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
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EPwm1Regs.TBCTL.bit.CLKDIV = BSP_PWM1_CLKDIV;
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EPwm1Regs.CMPCTL.bit.LOADAMODE = BSP_PWM1_LOADAMODE;
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EPwm1Regs.CMPCTL.bit.LOADBMODE = BSP_PWM1_LOADAMODE;
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#ifdef BSP_PWM1_IT_ENABLE
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EPwm1Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
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EPwm1Regs.ETSEL.bit.INTSEL = BSP_PWM1_INTSEL;
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EPwm1Regs.ETPS.bit.INTPRD = BSP_PWM1_INTPRD;
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/* Assigning ISR to PIE */
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PieVectTable.EPWM1_INT = &EPWM1_Isr;
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/* ENABLE Interrupt */
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#else
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EPwm1Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
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#endif
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#ifdef BSP_PWM1_ADC_TRIGGER
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EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
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EPwm1Regs.ETSEL.bit.SOCASEL = BSP_PWM1_SOCASEL; // Select SOC from zero
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EPwm1Regs.ETPS.bit.SOCAPRD = BSP_PWM1_SOCAPRD; // Generate pulse on 1st event
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#else
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EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
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#endif
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#ifdef BSP_PWM1_MASTER
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EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
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EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
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#else
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EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
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EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
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#endif
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#endif
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#ifdef BSP_USING_PWM2
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GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4; /* Disable pull-up on (EPWM2A) */
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GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4; /* Configure as EPWM2A */
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EPwm2Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
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EPwm2Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
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EPwm2Regs.TBCTL.bit.CTRMODE = BSP_PWM2_CTRMODE;
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EPwm2Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM2_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
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EPwm2Regs.TBCTL.bit.CLKDIV = BSP_PWM2_CLKDIV;
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EPwm2Regs.CMPCTL.bit.LOADAMODE = BSP_PWM2_LOADAMODE;
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EPwm2Regs.CMPCTL.bit.LOADBMODE = BSP_PWM2_LOADAMODE;
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#ifdef BSP_PWM2_IT_ENABLE
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EPwm2Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
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EPwm2Regs.ETSEL.bit.INTSEL = BSP_PWM2_INTSEL;
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EPwm2Regs.ETPS.bit.INTPRD = BSP_PWM2_INTPRD;
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/* Assigning ISR to PIE */
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PieVectTable.EPWM2_INT = &EPWM2_Isr;
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/* ENABLE Interrupt */
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#else
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EPwm2Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
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#endif
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#ifdef BSP_PWM2_ADC_TRIGGER
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EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
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EPwm2Regs.ETSEL.bit.SOCASEL = BSP_PWM2_SOCASEL; // Select SOC from zero
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EPwm2Regs.ETPS.bit.SOCAPRD = BSP_PWM2_SOCAPRD; // Generate pulse on 1st event
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#else
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EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
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#endif
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#ifdef BSP_PWM2_MASTER
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EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
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EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
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#else
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EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
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EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
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#endif
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#endif
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#ifdef BSP_USING_PWM3
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GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4; /* Disable pull-up on (EPWM3A) */
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GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4; /* Configure as EPWM3A */
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EPwm3Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
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EPwm3Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
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EPwm3Regs.TBCTL.bit.CTRMODE = BSP_PWM3_CTRMODE;
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EPwm3Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM3_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
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EPwm3Regs.TBCTL.bit.CLKDIV = BSP_PWM3_CLKDIV;
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EPwm3Regs.CMPCTL.bit.LOADAMODE = BSP_PWM3_LOADAMODE;
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EPwm3Regs.CMPCTL.bit.LOADBMODE = BSP_PWM3_LOADAMODE;
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#ifdef BSP_PWM3_IT_ENABLE
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EPwm3Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
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EPwm3Regs.ETSEL.bit.INTSEL = BSP_PWM3_INTSEL;
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EPwm3Regs.ETPS.bit.INTPRD = BSP_PWM3_INTPRD;
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/* Assigning ISR to PIE */
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PieVectTable.EPWM3_INT = &EPWM3_Isr;
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/* ENABLE Interrupt */
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#else
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EPwm3Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
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#endif
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#ifdef BSP_PWM3_ADC_TRIGGER
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EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
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EPwm3Regs.ETSEL.bit.SOCASEL = BSP_PWM3_SOCASEL; // Select SOC from zero
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EPwm3Regs.ETPS.bit.SOCAPRD = BSP_PWM3_SOCAPRD; // Generate pulse on 1st event
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#else
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EPwm3Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
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#endif
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#ifdef BSP_PWM3_MASTER
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EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
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EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
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#else
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EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
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EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
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#endif
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#endif
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#ifdef BSP_USING_PWM4
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GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4; /* Disable pull-up on (EPWM4A) */
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GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4; /* Configure as EPWM4A */
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EPwm4Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */
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EPwm4Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */
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EPwm4Regs.TBCTL.bit.CTRMODE = BSP_PWM4_CTRMODE;
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EPwm4Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM4_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/
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EPwm4Regs.TBCTL.bit.CLKDIV = BSP_PWM4_CLKDIV;
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EPwm4Regs.CMPCTL.bit.LOADAMODE = BSP_PWM4_LOADAMODE;
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EPwm4Regs.CMPCTL.bit.LOADBMODE = BSP_PWM4_LOADAMODE;
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#ifdef BSP_PWM4_IT_ENABLE
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EPwm4Regs.ETSEL.bit.INTEN = 1; /* Enable INT */
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EPwm4Regs.ETSEL.bit.INTSEL = BSP_PWM4_INTSEL;
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EPwm4Regs.ETPS.bit.INTPRD = BSP_PWM4_INTPRD;
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/* Assigning ISR to PIE */
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PieVectTable.EPWM4_INT = &EPWM4_Isr;
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/* ENABLE Interrupt */
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#else
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EPwm4Regs.ETSEL.bit.INTEN = 0; /* Disable INT */
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#endif
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#ifdef BSP_PWM4_ADC_TRIGGER
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EPwm4Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
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EPwm4Regs.ETSEL.bit.SOCASEL = BSP_PWM4_SOCASEL; // Select SOC from zero
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EPwm4Regs.ETPS.bit.SOCAPRD = BSP_PWM4_SOCAPRD; // Generate pulse on 1st event
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#else
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EPwm4Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
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#endif
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#ifdef BSP_PWM4_MASTER
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EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */
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EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
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#else
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EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */
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EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
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#endif
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#endif
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EDIS;
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return result;
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}
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int c28x_pwm_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(c28x_pwm_obj) / sizeof(c28x_pwm_obj[0]); i++)
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{
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/* pwm init */
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if (c28x_hw_pwm_init(&c28x_pwm_obj[i]) != RT_EOK)
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{
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LOG_E("%s init failed", c28x_pwm_obj[i].name);
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result = -RT_ERROR;
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return result;
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}
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else
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{
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LOG_D("%s init success", c28x_pwm_obj[i].name);
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/* register pwm device */
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if (rt_device_pwm_register(&c28x_pwm_obj[i].pwm_device, c28x_pwm_obj[i].name, &rt_pwm_ops, &c28x_pwm_obj[i]) == RT_EOK)
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{
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LOG_D("%s register success", c28x_pwm_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", c28x_pwm_obj[i].name);
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result = -RT_ERROR;
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}
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}
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}
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struct rt_pwm_configuration config_tmp1 =
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{
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.channel = CHANNEL_A,
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.period = BSP_PWM1_INIT_PERIOD,
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.pulse = BSP_PWM1_INIT_PULSE,
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.dead_time = BSP_PWM1_DB,
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.phase = 0,
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.complementary = RT_TRUE
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};
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drv_pwm_set(c28x_pwm_obj[0].pwm_regs,&config_tmp1);
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// config_tmp1.phase = BSP_PWM2_PHASE;
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// drv_pwm_set(c28x_pwm_obj[1].pwm_regs,&config_tmp1);
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// config_tmp1.phase = BSP_PWM3_PHASE;
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// drv_pwm_set(c28x_pwm_obj[2].pwm_regs,&config_tmp1);
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// config_tmp1.phase = BSP_PWM4_PHASE;
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// drv_pwm_set(c28x_pwm_obj[3].pwm_regs,&config_tmp1);
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return result;
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}
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INIT_DEVICE_EXPORT(c28x_pwm_init);
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#endif /* BSP_USING_PWM */
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