63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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* 2015-07-06 chinesebear modified for Loongson LS1C
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* 2019-12-04 Jiaxun Yang Add board config defines
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtconfig.h>
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#ifndef __ASSEMBLY__
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void rt_hw_board_init(void);
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#endif
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/*
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* SDRAM config
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*
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* Take IS42S16400 SDRAM chip as a example
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* The specfication is
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* Size 8MB
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* WIDTH: 16 bits
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* COL WIDTH: 8 bits, so we should take the 8 power of 2, it's 256
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* ROW WIDTH: 12 bits, so we take the 12 power of 2, it's 4K
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*
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* Please reference macro SD_PARA0 and SDRAM registers intruduction
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* in user's manual to edit the SDRAM config.
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*/
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#if defined(RT_LS1C_BAICAIBOARD)
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/* 8MByte IS42S16400 appeared in bacai_board V1.x V2.x */
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#define MEM_SIZE (0x800000)
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#define SDRAM_WIDTH (WIDTH_16)
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#define SDRAM_COL (COL_256)
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#define SDRAM_ROW (ROW_4K)
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#elif defined(RT_LS1C_OPENLOONGSON)
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/* 32MByte appeared in SmartLoong board */
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#define MEM_SIZE (0x2000000)
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#define SDRAM_WIDTH (WIDTH_16)
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#define SDRAM_COL (COL_512)
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#define SDRAM_ROW (ROW_8K)
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#else
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#error Unknown Board
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#endif
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/* Early Debug config */
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#define EARLY_DEBUG /* UART2 serial print debug in early stage */
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#define EARLY_DEBUG_BAUD (115200)
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/* Clock config */
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#define CPU_HZ (252 * 1000000)
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#define PLL_MULT (0x54) /* When external clock is 24Mhz PLL=504Mhz */
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#define SDRAM_DIV (0) /* SDRAM is CPU divided by 2*/
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#define CPU_DIV (2) /* CPU clock is PLL divided by 2 */
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#endif
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