413 lines
9.6 KiB
C
413 lines
9.6 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-11-11 GuEe-GUI the first version
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*/
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#ifndef __VIRTIO_GPU_H__
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#define __VIRTIO_GPU_H__
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#include <rtdef.h>
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#include <virtio.h>
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#define VIRTIO_GPU_QUEUE_CTRL 0
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#define VIRTIO_GPU_QUEUE_CURSOR 1
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#define VIRTIO_GPU_QUEUE_SIZE 32
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#define VIRTIO_GPU_F_VIRGL 0 /* VIRTIO_GPU_CMD_CTX_*, VIRTIO_GPU_CMD_*_3D */
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#define VIRTIO_GPU_F_EDID 1 /* VIRTIO_GPU_CMD_GET_EDID */
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#define VIRTIO_GPU_F_RESOURCE_UUID 2 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
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#define VIRTIO_GPU_F_RESOURCE_BLOB 3 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
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#define VIRTIO_GPU_F_CONTEXT_INIT 4 /* VIRTIO_GPU_CMD_CREATE_CONTEXT with context_init and multiple timelines */
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#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
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#define VIRTIO_GPU_FORMAT_BPP 32
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#define VIRTIO_GPU_FORMAT_PIXEL 4
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#define VIRTIO_GPU_CURSOR_WIDTH 64
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#define VIRTIO_GPU_CURSOR_HEIGHT 64
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#define VIRTIO_GPU_CURSOR_IMG_SIZE (VIRTIO_GPU_CURSOR_WIDTH * VIRTIO_GPU_CURSOR_HEIGHT * VIRTIO_GPU_FORMAT_PIXEL)
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#define VIRTIO_GPU_INVALID_PMODE_ID RT_UINT32_MAX
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/* GPU control */
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struct virtio_gpu_config
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{
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rt_uint32_t events_read;
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rt_uint32_t events_clear;
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rt_uint32_t num_scanouts; /* 1 ~ 16 */
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rt_uint32_t reserved;
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};
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enum virtio_gpu_ctrl_type
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{
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VIRTIO_GPU_UNDEFINED = 0,
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/* 2d commands */
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VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
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VIRTIO_GPU_CMD_RESOURCE_UNREF,
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VIRTIO_GPU_CMD_SET_SCANOUT,
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VIRTIO_GPU_CMD_RESOURCE_FLUSH,
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VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
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VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
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VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
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VIRTIO_GPU_CMD_GET_CAPSET_INFO,
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VIRTIO_GPU_CMD_GET_CAPSET,
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VIRTIO_GPU_CMD_GET_EDID,
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VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
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VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
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/* 3d commands */
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VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
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VIRTIO_GPU_CMD_CTX_DESTROY,
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VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
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VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
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VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
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VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
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VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
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VIRTIO_GPU_CMD_SUBMIT_3D,
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VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
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VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
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/* cursor commands */
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VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
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VIRTIO_GPU_CMD_MOVE_CURSOR,
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/* success responses */
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VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
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VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
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VIRTIO_GPU_RESP_OK_CAPSET_INFO,
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VIRTIO_GPU_RESP_OK_CAPSET,
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VIRTIO_GPU_RESP_OK_EDID,
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VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
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VIRTIO_GPU_RESP_OK_MAP_INFO,
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/* error responses */
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VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
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VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
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VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
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VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
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};
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#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
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struct virtio_gpu_ctrl_hdr
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{
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rt_uint32_t type;
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rt_uint32_t flags;
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rt_uint64_t fence_id;
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rt_uint32_t ctx_id;
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rt_uint8_t ring_idx;
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rt_uint8_t padding[3];
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};
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#define VIRTIO_GPU_MAX_SCANOUTS 16
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struct virtio_gpu_rect
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{
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rt_uint32_t x;
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rt_uint32_t y;
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rt_uint32_t width;
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rt_uint32_t height;
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};
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struct virtio_gpu_resp_display_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_display_one
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{
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struct virtio_gpu_rect r;
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rt_uint32_t enabled;
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rt_uint32_t flags;
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} pmodes[VIRTIO_GPU_MAX_SCANOUTS];
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};
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struct virtio_gpu_get_edid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t scanout;
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rt_uint32_t padding;
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};
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struct virtio_gpu_resp_edid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t size;
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rt_uint32_t padding;
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rt_uint8_t edid[1024];
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};
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enum virtio_gpu_formats
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{
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VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
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VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
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VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
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VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
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VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
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VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
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VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
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VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
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};
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struct virtio_gpu_resource_create_2d
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t format;
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rt_uint32_t width;
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rt_uint32_t height;
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};
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struct virtio_gpu_resource_unref
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t padding;
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};
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struct virtio_gpu_set_scanout
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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rt_uint32_t scanout_id;
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rt_uint32_t resource_id;
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};
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struct virtio_gpu_resource_flush
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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rt_uint32_t resource_id;
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rt_uint32_t padding;
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};
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struct virtio_gpu_transfer_to_host_2d
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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rt_uint64_t offset;
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rt_uint32_t resource_id;
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rt_uint32_t padding;
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};
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struct virtio_gpu_resource_attach_backing
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t nr_entries;
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};
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struct virtio_gpu_mem_entry
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{
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rt_uint64_t addr;
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rt_uint32_t length;
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rt_uint32_t padding;
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};
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struct virtio_gpu_resource_detach_backing
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t padding;
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};
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struct virtio_gpu_get_capset_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t capset_index;
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rt_uint32_t padding;
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};
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#define VIRTIO_GPU_CAPSET_VIRGL 1
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#define VIRTIO_GPU_CAPSET_VIRGL2 2
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#define VIRTIO_GPU_CAPSET_GFXSTREAM 3
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#define VIRTIO_GPU_CAPSET_VENUS 4
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#define VIRTIO_GPU_CAPSET_CROSS_DOMAIN 5
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struct virtio_gpu_resp_capset_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t capset_id;
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rt_uint32_t capset_max_version;
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rt_uint32_t capset_max_size;
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rt_uint32_t padding;
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};
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struct virtio_gpu_get_capset
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t capset_id;
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rt_uint32_t capset_version;
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};
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struct virtio_gpu_resp_capset
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint8_t capset_data[];
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};
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struct virtio_gpu_resource_assign_uuid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t padding;
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};
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struct virtio_gpu_resp_resource_uuid
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint8_t uuid[16];
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};
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#define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
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#define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
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#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
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#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
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#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
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#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
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struct virtio_gpu_resource_create_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t blob_mem;
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rt_uint32_t blob_flags;
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rt_uint32_t nr_entries;
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rt_uint64_t blob_id;
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rt_uint64_t size;
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};
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struct virtio_gpu_set_scanout_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_rect r;
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rt_uint32_t scanout_id;
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rt_uint32_t resource_id;
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rt_uint32_t width;
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rt_uint32_t height;
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rt_uint32_t format;
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rt_uint32_t padding;
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rt_uint32_t strides[4];
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rt_uint32_t offsets[4];
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};
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#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
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struct virtio_gpu_ctx_create
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t nlen;
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rt_uint32_t context_init;
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char debug_name[64];
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};
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struct virtio_gpu_resource_map_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t padding;
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rt_uint64_t offset;
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};
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#define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
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#define VIRTIO_GPU_MAP_CACHE_NONE 0x00
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#define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
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#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
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#define VIRTIO_GPU_MAP_CACHE_WC 0x03
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struct virtio_gpu_resp_map_info
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t map_info;
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rt_uint32_t padding;
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};
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struct virtio_gpu_resource_unmap_blob
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{
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struct virtio_gpu_ctrl_hdr hdr;
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rt_uint32_t resource_id;
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rt_uint32_t padding;
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};
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/* GPU cursor */
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struct virtio_gpu_cursor_pos
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{
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rt_uint32_t scanout_id;
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rt_uint32_t x;
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rt_uint32_t y;
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rt_uint32_t padding;
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};
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struct virtio_gpu_update_cursor
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{
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struct virtio_gpu_ctrl_hdr hdr;
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struct virtio_gpu_cursor_pos pos;
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rt_uint32_t resource_id;
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rt_uint32_t hot_x;
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rt_uint32_t hot_y;
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rt_uint32_t padding;
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};
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struct virtio_gpu_device
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{
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struct rt_device parent;
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struct virtio_device virtio_dev;
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/* Current display's info */
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struct virtio_gpu_display_one pmode;
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enum virtio_gpu_formats format;
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rt_uint32_t pmode_id;
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rt_uint32_t cursor_x, cursor_y;
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rt_uint32_t display_resource_id;
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rt_uint32_t cursor_resource_id;
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rt_uint32_t next_resource_id;
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/* Display framebuffer */
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struct rt_mutex rw_mutex;
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void *framebuffer;
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rt_uint32_t smem_len;
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/* Cursor image info */
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rt_bool_t cursor_enable;
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struct rt_mutex ops_mutex;
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rt_uint8_t cursor_img[VIRTIO_GPU_CURSOR_IMG_SIZE];
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/* GPU request info */
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struct virtio_gpu_resp_display_info gpu_request;
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struct
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{
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rt_bool_t ctrl_valid;
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rt_bool_t cursor_valid;
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struct virtio_gpu_update_cursor cursor_cmd;
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} info[VIRTIO_GPU_QUEUE_SIZE];
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};
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rt_err_t rt_virtio_gpu_init(rt_ubase_t *mmio_base, rt_uint32_t irq);
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enum
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{
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VIRTIO_DEVICE_CTRL_GPU_SET_PRIMARY = 0x20,
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VIRTIO_DEVICE_CTRL_GPU_CREATE_2D,
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VIRTIO_DEVICE_CTRL_CURSOR_SETUP,
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VIRTIO_DEVICE_CTRL_CURSOR_SET_IMG,
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VIRTIO_DEVICE_CTRL_CURSOR_MOVE,
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};
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#endif /* __VIRTIO_GPU_H__ */
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