530 lines
19 KiB
C
530 lines
19 KiB
C
/*
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* Copyright (c) 2021 - 2022 hpmicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Change Logs:
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* Date Author Notes
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* 2022-01-11 hpmicro First version
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* 2022-07-10 hpmicro Driver optimization for multiple instances
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*/
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#include <rtdevice.h>
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#ifdef BSP_USING_ETH
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#include <rtdbg.h>
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#include <netif/ethernetif.h>
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#include "board.h"
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#include "drv_enet.h"
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#include "hpm_soc_feature.h"
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#include "hpm_enet_soc_drv.h"
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#include "hpm_enet_drv.h"
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#define ETH_DEBUG
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#ifdef BSP_USING_ETH0
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT)
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__RW enet_rx_desc_t enet0_dma_rx_desc_tab[ENET0_RX_BUFF_COUNT] ; /* Ethernet0 Rx DMA Descriptor */
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT)
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__RW enet_tx_desc_t enet0_dma_tx_desc_tab[ENET0_TX_BUFF_COUNT] ; /* Ethernet0 Tx DMA Descriptor */
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT)
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__RW uint8_t enet0_rx_buff[ENET0_RX_BUFF_COUNT][ENET0_RX_BUFF_SIZE]; /* Ethernet0 Receive Buffer */
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT)
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__RW uint8_t enet0_tx_buff[ENET0_TX_BUFF_COUNT][ENET0_TX_BUFF_SIZE]; /* Ethernet0 Transmit Buffer */
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struct eth_device eth0_dev;
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static enet_device enet0_dev;
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static enet_buff_config_t enet0_rx_buff_cfg = {.buffer = (uint32_t)enet0_rx_buff,
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.count = ENET0_RX_BUFF_COUNT,
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.size = ENET0_RX_BUFF_SIZE
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};
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static enet_buff_config_t enet0_tx_buff_cfg = {.buffer = (uint32_t)enet0_tx_buff,
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.count = ENET0_TX_BUFF_COUNT,
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.size = ENET0_TX_BUFF_SIZE
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};
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static enet_ptp_time_t ptp_timestamp0 = {0, 0};
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static enet_ptp_config_t ptp_config0 = {.sub_sec_count_res = enet_ptp_count_res_low,
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.update_method = enet_ptp_time_fine_update,
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.addend = 0xffffffff,
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};
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static hpm_enet_t enet0 = {.name = "ETH0",
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.base = HPM_ENET0,
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.irq_num = IRQn_ENET0,
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.inf = BOARD_ENET0_INF,
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.eth_dev = ð0_dev,
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.enet_dev = &enet0_dev,
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.rx_buff_cfg = &enet0_rx_buff_cfg,
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.tx_buff_cfg = &enet0_tx_buff_cfg,
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.dma_rx_desc_tab = enet0_dma_rx_desc_tab,
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.dma_tx_desc_tab = enet0_dma_tx_desc_tab,
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.tx_delay = BOARD_ENET0_TX_DLY,
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.rx_delay = BOARD_ENET0_RX_DLY,
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.ptp_enable = true,
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.ptp_clk_src = BOARD_ENET0_PTP_CLOCK,
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.ptp_config = &ptp_config0,
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.ptp_timestamp = &ptp_timestamp0
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};
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#endif
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#ifdef BSP_USING_ETH1
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT)
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__RW enet_rx_desc_t enet1_dma_rx_desc_tab[ENET1_RX_BUFF_COUNT]; /* Ethernet1 Rx DMA Descriptor */
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT)
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__RW enet_tx_desc_t enet1_dma_tx_desc_tab[ENET1_TX_BUFF_COUNT]; /* Ethernet1 Tx DMA Descriptor */
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT)
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__RW uint8_t enet1_rx_buff[ENET1_RX_BUFF_COUNT][ENET1_RX_BUFF_SIZE]; /* Ethernet1 Receive Buffer */
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ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT)
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__RW uint8_t enet1_tx_buff[ENET1_TX_BUFF_COUNT][ENET1_TX_BUFF_SIZE]; /* Ethernet1 Transmit Buffer */
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struct eth_device eth1_dev;
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static enet_device enet1_dev;
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static enet_buff_config_t enet1_rx_buff_cfg = {.buffer = (uint32_t)enet1_rx_buff,
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.count = ENET1_RX_BUFF_COUNT,
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.size = ENET1_RX_BUFF_SIZE
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};
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static enet_buff_config_t enet1_tx_buff_cfg = {.buffer = (uint32_t)enet1_tx_buff,
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.count = ENET1_TX_BUFF_COUNT,
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.size = ENET1_TX_BUFF_SIZE
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};
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static enet_ptp_time_t ptp_timestamp1 = {0, 0};
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static enet_ptp_config_t ptp_config1 = {.sub_sec_count_res = enet_ptp_count_res_low,
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.update_method = enet_ptp_time_fine_update,
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.addend = 0xffffffff,
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};
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static hpm_enet_t enet1 = {.name = "ETH1",
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.base = HPM_ENET1,
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.irq_num = IRQn_ENET1,
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.inf = BOARD_ENET1_INF,
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.eth_dev = ð1_dev,
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.enet_dev = &enet1_dev,
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.rx_buff_cfg = &enet1_rx_buff_cfg,
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.tx_buff_cfg = &enet1_tx_buff_cfg,
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.dma_rx_desc_tab = enet1_dma_rx_desc_tab,
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.dma_tx_desc_tab = enet1_dma_tx_desc_tab,
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.int_refclk = BOARD_ENET1_INT_REF_CLK,
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.ptp_enable = true,
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.ptp_clk_src = BOARD_ENET1_PTP_CLOCK,
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.ptp_config = &ptp_config1,
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.ptp_timestamp = &ptp_timestamp1
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};
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#endif
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static hpm_enet_t *s_geths[] = {
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#ifdef BSP_USING_ETH0
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&enet0,
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#endif
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#ifdef BSP_USING_ETH1
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&enet1
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#endif
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};
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static hpm_stat_t hpm_enet_init(enet_device *init)
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{
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/* Initialize eth controller */
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enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, init->mask, init->dis_mask);
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if (init->media_interface == enet_inf_rmii)
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{
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/* Initialize reference clock */
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board_init_enet_rmii_reference_clock(init->instance, init->int_refclk);
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enet_rmii_enable_clock(init->instance, init->int_refclk);
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}
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/* Set RGMII clock delay */
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if (init->media_interface == enet_inf_rgmii)
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{
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enet_rgmii_enable_clock(init->instance);
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enet_rgmii_set_clock_delay(init->instance, init->tx_delay, init->rx_delay);
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}
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if (init->ptp_enable)
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{
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/* initialize Ethernet PTP Module */
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init->ptp_config.ssinc = ENET_ONE_SEC_IN_NANOSEC / clock_get_frequency(init->ptp_clk_src);
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enet_init_ptp(init->instance, &init->ptp_config);
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/* set the initial timestamp */
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enet_set_ptp_timestamp(init->instance, &init->ptp_timestamp);
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}
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/* enable irq */
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intc_m_enable_irq(init->irq_number);
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}
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static rt_err_t rt_hpm_eth_init(rt_device_t dev)
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{
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enet_device *enet_dev = (enet_device *)dev->user_data;
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/* Initialize GPIOs */
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board_init_enet_pins(enet_dev->instance);
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/* Reset an enet PHY */
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board_reset_enet_phy(enet_dev->instance);
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/* Initialize MAC and DMA */
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if (hpm_enet_init(enet_dev) == 0) {
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LOG_D("Ethernet control initialize successfully\n");
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}
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return RT_EOK;
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}
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static rt_err_t rt_hpm_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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return RT_EOK;
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}
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static rt_err_t rt_hpm_eth_close(rt_device_t dev)
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{
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return RT_EOK;
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}
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static rt_size_t rt_hpm_eth_read(rt_device_t dev, rt_off_t pos, void * buffer, rt_size_t size)
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{
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return 0;
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}
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static rt_size_t rt_hpm_eth_write(rt_device_t dev, rt_off_t pos, const void * buffer, rt_size_t size)
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{
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return 0;
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}
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static rt_err_t rt_hpm_eth_control(rt_device_t dev, int cmd, void * args)
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{
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uint8_t *mac;
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* read MAC address */
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if (args != NULL)
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{
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mac = (uint8_t *)args;
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mac[0] = MAC_ADDR0;
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mac[1] = MAC_ADDR1;
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mac[2] = MAC_ADDR2;
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mac[3] = MAC_ADDR3;
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mac[4] = MAC_ADDR4;
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mac[5] = MAC_ADDR5;
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SMEMCPY(args, mac, 6);
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}
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else
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{
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return -RT_ERROR;
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}
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break;
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default:
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break;
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}
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return RT_EOK;
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}
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static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p)
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{
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rt_err_t ret = RT_ERROR;
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uint32_t status;
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enet_device *enet_dev = (enet_device *)dev->user_data;
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uint32_t tx_buff_size = enet_dev->desc.tx_buff_cfg.size;
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struct pbuf *q;
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uint8_t *buffer;
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__IO enet_tx_desc_t *dma_tx_desc;
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uint32_t frame_length = 0;
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uint32_t buffer_offset = 0;
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uint32_t bytes_left_to_copy = 0;
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uint32_t payload_offset = 0;
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enet_tx_desc_t *tx_desc_list_cur = enet_dev->desc.tx_desc_list_cur;
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dma_tx_desc = tx_desc_list_cur;
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buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1);
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buffer_offset = 0;
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/* copy frame from pbufs to driver buffers */
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for (q = p; q != NULL; q = q->next)
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{
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/* Get bytes in current lwIP buffer */
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bytes_left_to_copy = q->len;
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payload_offset = 0;
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/* Check if the length of data to copy is bigger than Tx buffer size*/
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while ((bytes_left_to_copy + buffer_offset) > tx_buff_size)
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{
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/* Copy data to Tx buffer*/
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SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset),
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(uint8_t *)((uint8_t *)q->payload + payload_offset),
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tx_buff_size - buffer_offset);
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/* Point to next descriptor */
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dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc);
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/* Check if the buffer is available */
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if (dma_tx_desc->tdes0_bm.own != 0)
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{
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LOG_E("DMA tx desc buffer is not valid\n");
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return ERR_USE;
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}
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buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1);
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bytes_left_to_copy = bytes_left_to_copy - (tx_buff_size - buffer_offset);
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payload_offset = payload_offset + (tx_buff_size - buffer_offset);
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frame_length = frame_length + (tx_buff_size - buffer_offset);
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buffer_offset = 0;
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}
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/* Copy the remaining bytes */
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SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset),
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(uint8_t *)((uint8_t *)q->payload + payload_offset),
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bytes_left_to_copy);
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buffer_offset = buffer_offset + bytes_left_to_copy;
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frame_length = frame_length + bytes_left_to_copy;
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}
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/* Prepare transmit descriptors to give to DMA */
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LOG_D("The length of the transmitted frame: %d\n", frame_length);
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frame_length += 4;
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status = enet_prepare_transmission_descriptors(enet_dev->instance, &enet_dev->desc.tx_desc_list_cur, frame_length, enet_dev->desc.tx_buff_cfg.size);
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if (status != ENET_SUCCESS)
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{
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LOG_E("Ethernet controller transmit unsuccessfully: %d\n", status);
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}
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return ERR_OK;
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}
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static struct pbuf *rt_hpm_eth_rx(rt_device_t dev)
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{
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struct pbuf *p = NULL, *q = NULL;
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enet_device *enet_dev = (enet_device *)dev->user_data;
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uint32_t rx_buff_size = enet_dev->desc.rx_buff_cfg.size;
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uint16_t len = 0;
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uint8_t *buffer;
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enet_frame_t frame = {0, 0, 0};
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enet_rx_desc_t *dma_rx_desc;
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uint32_t buffer_offset = 0;
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uint32_t payload_offset = 0;
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uint32_t bytes_left_to_copy = 0;
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uint32_t i = 0;
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/* Get a received frame */
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frame = enet_get_received_frame_interrupt(&enet_dev->desc.rx_desc_list_cur,
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&enet_dev->desc.rx_frame_info,
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enet_dev->desc.rx_buff_cfg.count);
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/* Obtain the size of the packet and put it into the "len" variable. */
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len = frame.length;
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buffer = (uint8_t *)frame.buffer;
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LOG_D("The current received frame length : %d\n", len);
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if (len > 0)
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{
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/* allocate a pbuf chain of pbufs from the Lwip buffer pool */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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}
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if (p != NULL)
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{
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dma_rx_desc = frame.rx_desc;
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buffer_offset = 0;
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for (q = p; q != NULL; q = q->next)
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{
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bytes_left_to_copy = q->len;
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payload_offset = 0;
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/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
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while ((bytes_left_to_copy + buffer_offset) > rx_buff_size)
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{
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/* Copy data to pbuf */
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SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), (rx_buff_size - buffer_offset));
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/* Point to next descriptor */
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dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc);
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buffer = (uint8_t *)(dma_rx_desc->rdes2_bm.buffer1);
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bytes_left_to_copy = bytes_left_to_copy - (rx_buff_size - buffer_offset);
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payload_offset = payload_offset + (rx_buff_size - buffer_offset);
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buffer_offset = 0;
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}
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/* Copy remaining data in pbuf */
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SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), bytes_left_to_copy);
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buffer_offset = buffer_offset + bytes_left_to_copy;
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}
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}
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else
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{
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return NULL;
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}
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/* Release descriptors to DMA */
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/* Point to first descriptor */
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dma_rx_desc = frame.rx_desc;
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/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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for (i = 0; i < enet_dev->desc.rx_frame_info.seg_count; i++)
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{
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dma_rx_desc->rdes0_bm.own = 1;
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dma_rx_desc = (enet_rx_desc_t*)(dma_rx_desc->rdes3_bm.next_desc);
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}
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/* Clear Segment_Count */
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enet_dev->desc.rx_frame_info.seg_count = 0;
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return p;
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}
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static void eth_rx_callback(struct eth_device* dev)
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{
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rt_err_t result;
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result = eth_device_ready(dev);
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if (result != RT_EOK)
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{
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LOG_I("Receive callback error = %d\n", result);
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}
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}
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void isr_enet(hpm_enet_t *obj)
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{
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uint32_t status;
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status = obj->base->DMA_STATUS;
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if (ENET_DMA_STATUS_GLPII_GET(status)) {
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obj->base->DMA_STATUS |= ENET_DMA_STATUS_GLPII_SET(ENET_DMA_STATUS_GLPII_GET(status));
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}
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if (ENET_DMA_STATUS_RI_GET(status)) {
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obj->base->DMA_STATUS |= ENET_DMA_STATUS_RI_SET(ENET_DMA_STATUS_RI_GET(status));
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eth_rx_callback(obj->eth_dev);
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}
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}
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#ifdef BSP_USING_ETH0
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void isr_enet0(void)
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{
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isr_enet(&enet0);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_ENET0, isr_enet0)
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#endif
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#ifdef BSP_USING_ETH1
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void isr_enet1(void)
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{
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isr_enet(&enet1);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_ENET1, isr_enet1)
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#endif
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int rt_hw_eth_init(void)
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{
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rt_err_t err = RT_ERROR;
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for (uint32_t i = 0; i < ARRAY_SIZE(s_geths); i++)
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{
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/* Clear memory */
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memset((uint8_t *)s_geths[i]->dma_rx_desc_tab, 0x00, sizeof(enet_rx_desc_t) * s_geths[i]->rx_buff_cfg->count);
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memset((uint8_t *)s_geths[i]->dma_tx_desc_tab, 0x00, sizeof(enet_tx_desc_t) * s_geths[i]->tx_buff_cfg->count);
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memset((uint8_t *)s_geths[i]->rx_buff_cfg->buffer, 0x00, sizeof(s_geths[i]->rx_buff_cfg->size));
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memset((uint8_t *)s_geths[i]->tx_buff_cfg->buffer, 0x00, sizeof(s_geths[i]->tx_buff_cfg->size));
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/* Set list heads */
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s_geths[i]->enet_dev->desc.tx_desc_list_head = (enet_tx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)s_geths[i]->dma_tx_desc_tab);
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s_geths[i]->enet_dev->desc.rx_desc_list_head = (enet_rx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)s_geths[i]->dma_rx_desc_tab);
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s_geths[i]->enet_dev->desc.tx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, s_geths[i]->tx_buff_cfg->buffer);
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s_geths[i]->enet_dev->desc.tx_buff_cfg.count = s_geths[i]->tx_buff_cfg->count;
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s_geths[i]->enet_dev->desc.tx_buff_cfg.size = s_geths[i]->tx_buff_cfg->size;
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s_geths[i]->enet_dev->desc.rx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, s_geths[i]->rx_buff_cfg->buffer);
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s_geths[i]->enet_dev->desc.rx_buff_cfg.count = s_geths[i]->rx_buff_cfg->count;
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s_geths[i]->enet_dev->desc.rx_buff_cfg.size = s_geths[i]->rx_buff_cfg->size;
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|
|
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/* Set mac0 address */
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s_geths[i]->enet_dev->mac_config.mac_addr_high[0] = MAC_ADDR5 << 8 | MAC_ADDR4;
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s_geths[i]->enet_dev->mac_config.mac_addr_low[0] = MAC_ADDR3 << 24 | MAC_ADDR2 << 16 | MAC_ADDR1 << 8 | MAC_ADDR0;
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s_geths[i]->enet_dev->mac_config.valid_max_count = 1;
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|
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/* Set instance */
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s_geths[i]->enet_dev->instance = s_geths[i]->base;
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|
|
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/* Set media interface */
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s_geths[i]->enet_dev->media_interface = s_geths[i]->inf;
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|
|
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/* Set refclk */
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s_geths[i]->enet_dev->int_refclk = s_geths[i]->int_refclk;
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|
|
|
/* Set TX delay */
|
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s_geths[i]->enet_dev->tx_delay = s_geths[i]->tx_delay;
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|
|
|
/* Set RX delay */
|
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s_geths[i]->enet_dev->rx_delay = s_geths[i]->rx_delay;
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|
|
|
/* Set PTP function */
|
|
s_geths[i]->enet_dev->ptp_enable = s_geths[i]->ptp_enable;
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|
s_geths[i]->enet_dev->ptp_clk_src = s_geths[i]->ptp_clk_src;
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|
s_geths[i]->enet_dev->ptp_config = *s_geths[i]->ptp_config;
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s_geths[i]->enet_dev->ptp_timestamp = *s_geths[i]->ptp_timestamp;
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|
|
|
/* Set the interrupt enable mask */
|
|
s_geths[i]->enet_dev->mask = ENET_DMA_INTR_EN_NIE_SET(1) /* Enable normal interrupt summary */
|
|
| ENET_DMA_INTR_EN_RIE_SET(1); /* Enable receive interrupt */
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|
|
|
/* Set the interrupt disable mask */
|
|
s_geths[i]->enet_dev->dis_mask = ENET_INTR_MASK_RGSMIIIM_SET(1);
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|
|
|
/* Set the irq number */
|
|
s_geths[i]->enet_dev->irq_number = s_geths[i]->irq_num;
|
|
|
|
/* Set the parent parameters */
|
|
|
|
s_geths[i]->eth_dev->parent.init = rt_hpm_eth_init;
|
|
s_geths[i]->eth_dev->parent.open = rt_hpm_eth_open;
|
|
s_geths[i]->eth_dev->parent.close = rt_hpm_eth_close;
|
|
s_geths[i]->eth_dev->parent.read = rt_hpm_eth_read;
|
|
s_geths[i]->eth_dev->parent.write = rt_hpm_eth_write;
|
|
s_geths[i]->eth_dev->parent.control = rt_hpm_eth_control;
|
|
|
|
s_geths[i]->eth_dev->parent.user_data = s_geths[i]->enet_dev;
|
|
|
|
s_geths[i]->eth_dev->eth_rx = rt_hpm_eth_rx;
|
|
s_geths[i]->eth_dev->eth_tx = rt_hpm_eth_tx;
|
|
|
|
err = eth_device_init(s_geths[i]->eth_dev, s_geths[i]->name);
|
|
|
|
if (RT_EOK == err)
|
|
{
|
|
LOG_D("Ethernet device initialize successfully!\n");
|
|
}
|
|
else
|
|
{
|
|
LOG_D("Ethernet device initialize unsuccessfully!\n");
|
|
return err;
|
|
}
|
|
}
|
|
|
|
return err;
|
|
|
|
}
|
|
INIT_DEVICE_EXPORT(rt_hw_eth_init);
|
|
#endif /* BSP_USING_ETH */
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