438 lines
10 KiB
C
438 lines
10 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-07-14 Wayne First version
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*
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******************************************************************************/
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#include <rtthread.h>
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#include <rthw.h>
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#include <stdio.h>
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#include "drv_common.h"
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#include "board.h"
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#include "drv_uart.h"
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#define LOG_TAG "drv.common"
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#undef DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL LOG_LVL_DBG
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#define DBG_COLOR
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#include <rtdbg.h>
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#if defined(USE_MA35D1_AARCH32)
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#define NORMAL_MEM_UNCACHED (SHARED|AP_RW|DOMAIN0|STRONGORDER|DESC_SEC)
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/*
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MMU TLB setting:
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0xFFFFFFFF ----------------------------
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| 1GB DDR(non-cacheable) |
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0xC0000000 ----------------------------
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| 1GB DDR(cacheable) |
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0x80000000 ----------------------------
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| DEVICE_MEM |
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| |
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0x00000000 ----------------------------
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*/
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struct mem_desc platform_mem_desc[] =
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{
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{0x00000000, 0x7FFFFFFF, 0x00000000, DEVICE_MEM}, // Peripherals
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{0x80000000, DDR_LIMIT_SIZE - 1, 0x80000000, NORMAL_MEM}, // 1GB DDR, cacheable
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{0xC0000000, 0xFFFFFFFF, 0x80000000, NORMAL_MEM_UNCACHED} // 1GB DDR, non-cacheable
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};
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
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#endif
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static void nu_mmu_initialize(void)
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{
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#if defined(USE_MA35D1_AARCH64)
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mmu_init();
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/* device memory 0x0000_0000 - 0x3FFF_FFFF */
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armv8_map(0x00000000, 0x00000000, 0x40000000, MEM_ATTR_IO);
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/* device memory 0x4000_0000 - 0x7FFF_FFFF */
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armv8_map(0x40000000, 0x40000000, 0x40000000, MEM_ATTR_IO);
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/* system memory 0x8000_0000 - 0xFFFF_FFFF */
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armv8_map(0x80000000, 0x80000000, 0x80000000, MEM_ATTR_MEMORY);
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mmu_enable();
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#endif
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}
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#if !defined(USE_MA35D1_SUBM)
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volatile uint32_t secondary_cpu_entry __attribute__((aligned(32))) = 0;
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static rt_uint32_t timerStep;
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void rt_hw_systick_isr(int vector, void *parameter)
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{
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gtimer_set_load_value(timerStep);
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rt_tick_increase();
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}
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int rt_hw_systick_init(void)
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{
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rt_hw_interrupt_install(NonSecPhysicalTimer_IRQn, rt_hw_systick_isr, RT_NULL, "systick");
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rt_hw_interrupt_umask(NonSecPhysicalTimer_IRQn);
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timerStep = gtimer_get_counter_frequency();
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timerStep /= RT_TICK_PER_SECOND;
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gtimer_set_load_value(timerStep);
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gtimer_set_control(1);
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return 0;
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}
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void nu_sspcc_init(void)
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{
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int i, j;
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CLK->APBCLK2 |= CLK_APBCLK2_SSPCCEN_Msk;
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/* Set all GPIO security set to TZNS. */
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for (i = 0; i < 16; i++)
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{
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for (j = 0; j < 14; j++)
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{
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SSPCC_SetRealm_GPIO(GPIO_BASE + (j * 0x40), i, SSPCC_SSET_TZNS);
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}
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}
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}
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void nu_ssmcc_init(void)
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{
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CLK->APBCLK2 |= CLK_APBCLK2_SSMCCEN_Msk;
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/* set region 0 to secure region, non-secure and m4 all can access */
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SSMCC_SetRegion0(SSMCC_SECURE_READ | SSMCC_SECURE_WRITE | SSMCC_NONSECURE_READ | SSMCC_NONSECURE_WRITE | SSMCC_M4NS_READ | SSMCC_M4NS_WRITE);
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}
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void nu_ddr_init(void)
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{
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UMCTL2->PCTRL_0 = UMCTL2_PCTRL_0_port_en_Msk; //[0x0490]
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UMCTL2->PCTRL_1 = UMCTL2_PCTRL_1_port_en_Msk; //[0x0540]
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UMCTL2->PCTRL_2 = UMCTL2_PCTRL_2_port_en_Msk; //[0x05f0]
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UMCTL2->PCTRL_3 = UMCTL2_PCTRL_3_port_en_Msk; //[0x06a0]
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UMCTL2->PCTRL_4 = UMCTL2_PCTRL_4_port_en_Msk; //[0x0750]
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UMCTL2->PCTRL_5 = UMCTL2_PCTRL_5_port_en_Msk; //[0x0800]
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UMCTL2->PCTRL_6 = UMCTL2_PCTRL_6_port_en_Msk; //[0x08b0]
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UMCTL2->PCTRL_7 = UMCTL2_PCTRL_7_port_en_Msk; //[0x0960]
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}
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void rt_hw_us_delay(rt_uint32_t us)
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{
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rt_uint32_t ticks;
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volatile rt_uint32_t told, tnow, tcnt = 0;
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rt_uint32_t cmp = timerStep; // 12000 count / 1ms
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ticks = us * (cmp / 1000); // us * 12(count/1us)
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told = gtimer_get_current_value();
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while (1)
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{
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/* Timer counter is increment. */
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tnow = gtimer_get_current_value();
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if (tnow != told)
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{
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/* 0 -- now === old -------- cmp */
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if (tnow < told)
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{
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tcnt += (told - tnow);
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}
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else
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{
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/* 0 == old --- new ======== cmp */
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tcnt += (cmp - tnow + told);
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}
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told = tnow;
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/* Timeout */
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if (tcnt >= ticks)
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{
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break;
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}
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}
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__NOP();
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}
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} /* rt_hw_us_delay */
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#else
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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int rt_hw_systick_init(void)
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{
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/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
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SystemCoreClockUpdate();
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/* Configure SysTick */
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SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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return 0;
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}
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/**
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* The time delay function.
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*
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* @param microseconds.
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*/
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void rt_hw_us_delay(rt_uint32_t us)
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{
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rt_uint32_t ticks;
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rt_uint32_t told, tnow, tcnt = 0;
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rt_uint32_t reload = SysTick->LOAD;
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ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
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told = SysTick->VAL;
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while (1)
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{
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tnow = SysTick->VAL;
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if (tnow != told)
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{
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if (tnow < told)
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{
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tcnt += told - tnow;
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}
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else
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{
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tcnt += reload - tnow + told;
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}
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told = tnow;
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if (tcnt >= ticks)
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{
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break;
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}
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}
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}
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}
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#endif
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void devmem(int argc, char *argv[])
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{
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volatile unsigned int u32Addr;
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unsigned int value = 0, mode = 0;
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if (argc < 2 || argc > 3)
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{
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goto exit_devmem;
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}
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if (argc == 3)
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{
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if (sscanf(argv[2], "0x%x", &value) != 1)
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goto exit_devmem;
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mode = 1; //Write
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}
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if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
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goto exit_devmem;
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else if (u32Addr & (4 - 1))
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goto exit_devmem;
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if (mode)
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{
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*((volatile uint32_t *)u32Addr) = value;
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}
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rt_kprintf("0x%08x\n", *((volatile uint32_t *)u32Addr));
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return;
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exit_devmem:
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rt_kprintf("Read: devmem <physical address in hex>\n");
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rt_kprintf("Write: devmem <physical address in hex> <value in hex format>\n");
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return;
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}
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MSH_CMD_EXPORT(devmem, dump device registers);
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void devmem2(int argc, char *argv[])
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{
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volatile unsigned int u32Addr;
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unsigned int value = 0, word_count = 1;
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if (argc < 2 || argc > 3)
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{
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goto exit_devmem;
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}
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if (argc == 3)
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{
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if (sscanf(argv[2], "%d", &value) != 1)
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goto exit_devmem;
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word_count = value;
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}
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if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
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goto exit_devmem;
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else if (u32Addr & (4 - 1))
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goto exit_devmem;
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if (word_count > 0)
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{
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LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t));
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}
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return;
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exit_devmem:
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rt_kprintf("devmem2: <physical address in hex> <count in dec>\n");
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return;
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}
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MSH_CMD_EXPORT(devmem2, dump device registers);
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void idle_wfi(void)
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{
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#if defined(USE_MA35D1_SUBM)
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__WFI();
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#else
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asm volatile("wfi");
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#endif
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}
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extern void nu_clock_dump(void);
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extern void nu_clock_raise(void);
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rt_weak void nutool_pincfg_init(void)
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{
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}
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/**
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* This function will initial board.
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*/
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rt_weak void rt_hw_board_init(void)
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{
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/* Unlock protected registers */
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SYS_UnlockReg();
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#if !defined(USE_MA35D1_SUBM)
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/* initialize SSPCC */
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nu_sspcc_init();
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/* initialize SSMCC */
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nu_ssmcc_init();
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/* initialize UMCTL2 */
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nu_ddr_init();
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#endif
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/* initialize base clock */
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nu_clock_init();
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/* initialize peripheral pin function */
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nutool_pincfg_init();
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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/* initialize MMU */
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nu_mmu_initialize();
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#if defined(RT_USING_HEAP)
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rt_system_heap_init((void *)BOARD_HEAP_START, (void *)BOARD_HEAP_END);
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#endif
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/* initialize uart */
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rt_hw_uart_init();
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#if defined(RT_USING_CONSOLE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#if !defined(USE_MA35D1_SUBM)
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#if !defined(USE_MA35D1_AARCH64)
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//TOFIX
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nu_clock_raise();
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#endif
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nu_clock_dump();
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#endif
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#if defined(RT_USING_HEAP)
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/* Dump heap information */
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rt_kprintf("Heap: Begin@%08x, END@%08x, SIZE: %d KiB\n", BOARD_HEAP_START, BOARD_HEAP_END, ((rt_uint32_t)BOARD_HEAP_END - (rt_uint32_t)BOARD_HEAP_START) / 1024);
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#endif
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/* initialize systick */
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rt_hw_systick_init();
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rt_thread_idle_sethook(idle_wfi);
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#if defined(RT_USING_COMPONENTS_INIT)
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rt_components_board_init();
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#endif
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#if defined(RT_USING_SMP)
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/* install IPI handle */
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rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
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rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
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rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
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#endif
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}
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#if defined(RT_USING_SMP)
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extern void secondary_cpu_start(void);
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void set_secondary_cpu_boot_address(void)
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{
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secondary_cpu_entry = (uint32_t)&secondary_cpu_start;
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rt_kprintf("Wake up cpu-1 goto -> 0x%08x\n", secondary_cpu_entry);
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}
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void rt_hw_secondary_cpu_up(void)
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{
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rt_uint32_t i;
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rt_uint32_t cpu_mask;
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rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n");
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set_secondary_cpu_boot_address();
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/* Flush to memory */
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rt_cpu_dcache_clean_flush();
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for (i = 1; i < RT_CPUS_NR; i++)
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{
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rt_kprintf("Bring up cpu-%d\r\n", i);
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cpu_mask = 1 << i;
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__asm__ volatile("dsb" ::
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: "memory");
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__asm__ volatile("isb" ::
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: "memory");
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__asm__ volatile("sev");
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rt_hw_ipi_send(RT_SCHEDULE_IPI, cpu_mask);
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}
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}
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void secondary_cpu_c_start(void)
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{
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rt_kprintf("[%s] cpu-%d\r\n", __func__, rt_hw_cpu_id());
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rt_hw_vector_init();
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rt_hw_spin_lock(&_cpus_lock);
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arm_gic_cpu_init(0, platform_get_gic_cpu_base());
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rt_hw_systick_init();
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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asm volatile("wfe" ::
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: "memory", "cc");
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}
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#endif
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