115 lines
2.1 KiB
C
115 lines
2.1 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-09-06 勤为本 first version
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* 2021-02-02 michael5hzg@gmail.com adapt to ls1b
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*/
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#include "rtconfig.h"
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#include "ls1b_regs.h"
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#include "ls1b_public.h"
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// 晶振的频率
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#define AHB_CLK (RT_OSC_CLK)
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#define APB_CLK (AHB_CLK)
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#define DIV_DC_EN (0x1 << 31)
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#define DIV_DC (0x1f << 26)
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#define DIV_CPU_EN (0x1 << 25)
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#define DIV_CPU (0x1f << 20)
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#define DIV_DDR_EN (0x1 << 19)
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#define DIV_DDR (0x1f << 14)
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#define DIV_DC_SHIFT 26
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#define DIV_CPU_SHIFT 20
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#define DIV_DDR_SHIFT 14
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/*
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* 获取PLL频率
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* @ret PLL频率
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*/
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unsigned long clk_get_pll_rate(void)
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{
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unsigned int ctrl;
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unsigned long pll_rate = 0;
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ctrl = reg_read_32((volatile unsigned int *)LS1B_START_FREQ);
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pll_rate = (12 + (ctrl & 0x3f)) * APB_CLK / 2
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+ ((ctrl >> 8) & 0x3ff) * APB_CLK / 1024 / 2;
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return pll_rate;
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}
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/*
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* 获取CPU频率
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* @ret CPU频率
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*/
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unsigned long clk_get_cpu_rate(void)
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{
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unsigned long pll_rate, cpu_rate;
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unsigned int ctrl;
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pll_rate = clk_get_pll_rate();
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ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
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cpu_rate = pll_rate / ((ctrl & DIV_CPU) >> DIV_CPU_SHIFT);
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return cpu_rate;
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}
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/*
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* 获取DDR频率
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* @ret DDR频率
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*/
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unsigned long clk_get_ddr_rate(void)
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{
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unsigned long pll_rate, ddr_rate;
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unsigned int ctrl;
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pll_rate = clk_get_pll_rate();
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ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
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ddr_rate = pll_rate / ((ctrl & DIV_DDR) >> DIV_DDR_SHIFT);
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return ddr_rate;
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}
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/*
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* 获取APB频率
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* @ret APB频率
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*/
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unsigned long clk_get_apb_rate(void)
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{
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return clk_get_ddr_rate() / 2;
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}
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/*
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* 获取DC频率
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* @ret DC频率
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*/
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unsigned long clk_get_dc_rate(void)
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{
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unsigned long pll_rate, dc_rate;
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unsigned int ctrl;
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pll_rate = clk_get_pll_rate();
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ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
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dc_rate = pll_rate ;
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return dc_rate;
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}
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