320 lines
8.2 KiB
C
320 lines
8.2 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-26 huanghe first commit
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* 2022-10-26 zhugengyu support aarch64
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* 2023-04-13 zhugengyu support RT-Smart
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* 2023-07-27 zhugengyu update aarch32 gtimer usage
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*
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*/
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#include "rtconfig.h"
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#include <rthw.h>
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#include <rtthread.h>
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#include <mmu.h>
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#include <mm_aspace.h> /* TODO: why need application space when RT_SMART off */
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#include <mm_page.h>
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#ifdef RT_USING_SMART
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#include <page.h>
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#include <lwp_arch.h>
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#endif
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#include <gicv3.h>
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#if defined(TARGET_ARMV8_AARCH64)
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#include <psci.h>
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#include <gtimer.h>
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#include <cpuport.h>
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#else
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#include <gtimer.h>
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#endif
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#include <interrupt.h>
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#include <board.h>
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#include "fearly_uart.h"
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#include "fcpu_info.h"
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#include "fiopad.h"
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#ifdef RT_USING_SMP
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#include "fpsci.h"
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#endif
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extern FIOPadCtrl iopad_ctrl;
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uintptr flsd_config_base = FLSD_CONFIG_BASE;
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/* mmu config */
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extern struct mem_desc platform_mem_desc[];
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extern const rt_uint32_t platform_mem_desc_size;
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void idle_wfi(void)
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{
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asm volatile("wfi");
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}
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/**
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* This function will initialize board
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*/
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extern size_t MMUTable[];
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rt_region_t init_page_region =
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{
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PAGE_START,
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PAGE_END
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};
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void FIOMuxInit(void)
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{
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FIOPadCfgInitialize(&iopad_ctrl, FIOPadLookupConfig(FIOPAD0_ID));
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#ifdef RT_USING_SMART
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iopad_ctrl.config.base_address = (uintptr)rt_ioremap((void *)iopad_ctrl.config.base_address, 0x2000);
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#endif
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return;
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}
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#if defined(TARGET_ARMV8_AARCH64) /* AARCH64 */
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/* aarch64 use kernel gtimer */
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#else /* AARCH32 */
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/* aarch32 implment gtimer by bsp */
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static rt_uint32_t timer_step;
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#define CNTP_CTL_ENABLE (1U << 0) /* Enables the timer */
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#define CNTP_CTL_IMASK (1U << 1) /* Timer interrupt mask bit */
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#define CNTP_CTL_ISTATUS (1U << 2) /* The status of the timer */
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void GenericTimerInterruptEnable(u32 id)
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{
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u64 ctrl = gtimer_get_control();
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if (ctrl & CNTP_CTL_IMASK)
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{
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ctrl &= ~CNTP_CTL_IMASK;
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gtimer_set_control(ctrl);
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}
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}
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void GenericTimerStart(u32 id)
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{
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u32 ctrl = gtimer_get_control(); /* get CNTP_CTL */
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if (!(ctrl & CNTP_CTL_ENABLE))
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{
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ctrl |= CNTP_CTL_ENABLE; /* enable gtimer if off */
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gtimer_set_control(ctrl); /* set CNTP_CTL */
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}
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}
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void rt_hw_timer_isr(int vector, void *parameter)
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{
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gtimer_set_load_value(timer_step);
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rt_tick_increase();
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}
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int rt_hw_timer_init(void)
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{
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rt_hw_interrupt_install(GENERIC_TIMER_NS_IRQ_NUM, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(GENERIC_TIMER_NS_IRQ_NUM);
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timer_step = gtimer_get_counter_frequency();
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FASSERT_MSG((timer_step > 1000000), "invalid freqency %ud", timer_step);
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timer_step /= RT_TICK_PER_SECOND;
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gtimer_set_load_value(timer_step);
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GenericTimerInterruptEnable(GENERIC_TIMER_ID0);
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GenericTimerStart(GENERIC_TIMER_ID0);
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_timer_init);
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#endif
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#ifdef RT_USING_SMP
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
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#endif
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#if defined(TARGET_ARMV8_AARCH64)
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void rt_hw_board_aarch64_init(void)
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{
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/* AARCH64 */
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#if defined(RT_USING_SMART)
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/* 1. init rt_kernel_space table (aspace.start = KERNEL_VADDR_START , aspace.size = ), 2. init io map range (rt_ioremap_start \ rt_ioremap_size) 3. */
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rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
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#else
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rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x80000000, 0x10000000, MMUTable, 0);
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#endif
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rt_page_init(init_page_region);
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rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
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/* init memory pool */
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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rt_hw_interrupt_init();
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rt_hw_gtimer_init();
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FEarlyUartProbe();
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FIOMuxInit();
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#ifdef RT_USING_SMART
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#if defined(FLSD_CONFIG_BASE)
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flsd_config_base = (uintptr)rt_ioremap((void *)flsd_config_base, 0x1000);
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#endif
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#endif
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/* compoent init */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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/* shell init */
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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rt_thread_idle_sethook(idle_wfi);
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#ifdef RT_USING_SMP
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FPsciInit();
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/* install IPI handle */
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rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
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rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
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rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
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#endif
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}
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#else
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void rt_hw_board_aarch32_init(void)
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{
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#if defined(RT_USING_SMART)
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/* set io map range is 0xf0000000 ~ 0x10000000 , Memory Protection start address is 0xf0000000 - rt_mpr_size */
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rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000, MMUTable, PV_OFFSET);
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rt_page_init(init_page_region);
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/* rt_kernel_space 在start_gcc.S 中被初始化，此函数将iomap 空间放置在kernel space 上 */
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rt_hw_mmu_ioremap_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000);
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/* */
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arch_kuser_init(&rt_kernel_space, (void *)0xffff0000);
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#else
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/*
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map kernel space memory (totally 1GB = 0x10000000), pv_offset = 0 if not RT_SMART:
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0x80000000 ~ 0x80100000: kernel stack
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0x80100000 ~ __bss_end: kernel code and data
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*/
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rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x80000000, 0x10000000, MMUTable, 0);
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rt_hw_mmu_ioremap_init(&rt_kernel_space, (void *)0x80000000, 0x10000000);
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#endif
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/* init memory pool */
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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extern int rt_hw_cpu_id(void);
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u32 cpu_id, cpu_offset = 0;
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GetCpuId(&cpu_id);
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#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
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cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
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#endif
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rt_uint32_t redist_addr = 0;
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FEarlyUartProbe();
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FIOMuxInit();
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#if defined(RT_USING_SMART)
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redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128 * 1024);
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#if defined(FLSD_CONFIG_BASE)
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flsd_config_base = (uintptr)rt_ioremap((void *)flsd_config_base, 0x1000);
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#endif
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#else
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redist_addr = GICV3_RD_BASE_ADDR;
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#endif
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arm_gic_redist_address_set(0, redist_addr + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
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#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
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#if RT_CPUS_NR == 2
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arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
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#elif RT_CPUS_NR == 3
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arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr, 2);
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#elif RT_CPUS_NR == 4
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arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr, 2);
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arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3);
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#endif
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#else
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#if RT_CPUS_NR == 2
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arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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#elif RT_CPUS_NR == 3
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arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
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#elif RT_CPUS_NR == 4
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arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
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arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
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#endif
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#endif
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rt_hw_interrupt_init();
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/* compoent init */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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/* shell init */
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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rt_thread_idle_sethook(idle_wfi);
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#ifdef RT_USING_SMP
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FPsciInit();
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/* install IPI handle */
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rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
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rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
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rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
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#endif
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}
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#endif
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/**
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* This function will initialize hardware board
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*/
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void rt_hw_board_init(void)
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{
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#if defined(TARGET_ARMV8_AARCH64)
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rt_hw_board_aarch64_init();
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#else
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rt_hw_board_aarch32_init();
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#endif
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}
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