356 lines
9.2 KiB
ArmAsm
356 lines
9.2 KiB
ArmAsm
/* ******************** (C) COPYRIGHT 2017 MindMotion ******************** */
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/* File Name : startup_mm32L0xx.s */
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/* Author : AE Team */
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/* Version : V2.0.0 */
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/* Date : 22/08/2017 */
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/* Description : MM32L0xx Medium-density devices vector table for */
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/* GCC toolchain. */
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/* This module performs: */
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/* - Set the initial SP */
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/* - Set the initial PC == __iar_program_start, */
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/* - Set the vector table entries with the exceptions*/
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/* ISR address */
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/* - Configure the system clock */
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/* - Branches to main in the C library (which */
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/* eventually calls main()). */
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/* After Reset the Cortex-M0 processor is in Thread */
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/* mode, priority is Privileged, and the Stack is set*/
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/* to Main. */
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/* ************************************************************************/
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/* The vector table is normally located at address 0. When debugging in RAM, it can be located in RAM, aligned to at least 2^6. The name "__vector_table" has special meaning for C-SPY: it is where the SP start value is found, and the NVIC vector table register (VTOR) is initialized to this address if != 0. */
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/* Cortex-M version */
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.syntax unified
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.cpu cortex-m0
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.fpu softvfp
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.thumb
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.global __vector_table
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.word _sidata
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.word _sdata
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.word _edata
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.word _sbss
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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msr msp, r0
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/*Check if boot space corresponds to test memory*/
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ldr r0, =0x00000004
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ldr r1, [r0]
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lsrs r1, r1, #24
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ldr r2, =0x1F
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cmp r1, r2
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bne ApplicationStart
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/*SYSCFG clock enable*/
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ldr r0, =0x40021018
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ldr r1, =0x00000001
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str r1, [r0]
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/* Set CFGR1 register with flash memory remap at address 0 */
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ldr r0, =0x40010000
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ldr r1, =0x00000000
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str r1, [r0]
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ApplicationStart:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/* Vector Table Mapped to Address 0 at Reset */
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.section .isr_vector, "a", %progbits
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.type __vector_table, %object
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.size __vector_table, .-__vector_table
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__vector_table:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word 0
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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/* External Interrupts */
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.word WWDG_IRQHandler
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.word PVD_IRQHandler
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.word RTC_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_CRS_IRQHandler
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.word EXTI0_1_IRQHandler
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.word EXTI2_3_IRQHandler
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.word EXTI4_15_IRQHandler
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.word 0
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_3_IRQHandler
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.word DMA1_Channel4_5_IRQHandler
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.word ADC_COMP_IRQHandler
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.word TIM1_BRK_UP_TRG_COM_IRQHandler
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.word TIM1_CC_IRQHandler
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.word TIM2_IRQHandler
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.word TIM3_IRQHandler
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.word 0
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.word 0
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.word TIM14_IRQHandler
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.word 0
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.word TIM16_IRQHandler
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.word TIM17_IRQHandler
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.word I2C1_IRQHandler
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.word 0
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.word SPI1_IRQHandler
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.word SPI2_IRQHandler
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.word UART1_IRQHandler
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.word UART2_IRQHandler
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.word AES_IRQHandler
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.word CAN_IRQHandler
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.word USB_IRQHandler
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/* Dummy Exception Handlers (infinite loops which can be modified) */
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.section .text.NMI_Handler
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.weak NMI_Handler
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.type NMI_Handler, %function
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NMI_Handler:
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b NMI_Handler
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.section .text.HardFault_Handler
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.weak HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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b HardFault_Handler
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.section .text.SVC_Handler
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.weak SVC_Handler
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.type SVC_Handler, %function
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SVC_Handler:
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b SVC_Handler
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.section .text.PendSV_Handler
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.weak PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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b PendSV_Handler
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.section .text.SysTick_Handler
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.weak SysTick_Handler
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.type SysTick_Handler, %function
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SysTick_Handler:
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b SysTick_Handler
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.section .text.WWDG_IRQHandler
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.weak WWDG_IRQHandler
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.type WWDG_IRQHandler, %function
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WWDG_IRQHandler:
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b WWDG_IRQHandler
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.section .text.PVD_IRQHandler
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.weak PVD_IRQHandler
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.type PVD_IRQHandler, %function
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PVD_IRQHandler:
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b PVD_IRQHandler
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.section .text.RTC_IRQHandler
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.weak RTC_IRQHandler
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.type RTC_IRQHandler, %function
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RTC_IRQHandler:
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b RTC_IRQHandler
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.section .text.FLASH_IRQHandler
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.weak FLASH_IRQHandler
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.type FLASH_IRQHandler, %function
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FLASH_IRQHandler:
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b FLASH_IRQHandler
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.section .text.RCC_CRS_IRQHandler
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.weak RCC_CRS_IRQHandler
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.type RCC_CRS_IRQHandler, %function
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RCC_CRS_IRQHandler:
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b RCC_CRS_IRQHandler
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.section .text.EXTI0_1_IRQHandler
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.weak EXTI0_1_IRQHandler
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.type EXTI0_1_IRQHandler, %function
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EXTI0_1_IRQHandler:
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b EXTI0_1_IRQHandler
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.section .text.EXTI2_3_IRQHandler
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.weak EXTI2_3_IRQHandler
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.type EXTI2_3_IRQHandler, %function
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EXTI2_3_IRQHandler:
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b EXTI2_3_IRQHandler
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.section .text.EXTI4_15_IRQHandler
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.weak EXTI4_15_IRQHandler
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.type EXTI4_15_IRQHandler, %function
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EXTI4_15_IRQHandler:
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b EXTI4_15_IRQHandler
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.section .text.DMA1_Channel1_IRQHandler
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.weak DMA1_Channel1_IRQHandler
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.type DMA1_Channel1_IRQHandler, %function
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DMA1_Channel1_IRQHandler:
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b DMA1_Channel1_IRQHandler
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.section .text.DMA1_Channel2_3_IRQHandler
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.weak DMA1_Channel2_3_IRQHandler
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.type DMA1_Channel2_3_IRQHandler, %function
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DMA1_Channel2_3_IRQHandler:
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b DMA1_Channel2_3_IRQHandler
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.section .text.DMA1_Channel4_5_IRQHandler
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.weak DMA1_Channel4_5_IRQHandler
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.type DMA1_Channel4_5_IRQHandler, %function
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DMA1_Channel4_5_IRQHandler:
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b DMA1_Channel4_5_IRQHandler
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.section .text.ADC_COMP_IRQHandler
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.weak ADC_COMP_IRQHandler
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.type ADC_COMP_IRQHandler, %function
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ADC_COMP_IRQHandler:
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b ADC_COMP_IRQHandler
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.section .text.TIM1_BRK_UP_TRG_COM_IRQHandler
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.weak TIM1_BRK_UP_TRG_COM_IRQHandler
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.type TIM1_BRK_UP_TRG_COM_IRQHandler, %function
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TIM1_BRK_UP_TRG_COM_IRQHandler:
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b TIM1_BRK_UP_TRG_COM_IRQHandler
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.section .text.TIM1_CC_IRQHandler
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.weak TIM1_CC_IRQHandler
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.type TIM1_CC_IRQHandler, %function
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TIM1_CC_IRQHandler:
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b TIM1_CC_IRQHandler
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.section .text.TIM2_IRQHandler
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.weak TIM2_IRQHandler
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.type TIM2_IRQHandler, %function
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TIM2_IRQHandler:
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b TIM2_IRQHandler
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.section .text.TIM3_IRQHandler
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.weak TIM3_IRQHandler
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.type TIM3_IRQHandler, %function
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TIM3_IRQHandler:
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b TIM3_IRQHandler
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.section .text.TIM14_IRQHandler
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.weak TIM14_IRQHandler
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.type TIM14_IRQHandler, %function
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TIM14_IRQHandler:
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b TIM14_IRQHandler
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.section .text.TIM16_IRQHandler
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.weak TIM16_IRQHandler
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.type TIM16_IRQHandler, %function
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TIM16_IRQHandler:
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b TIM16_IRQHandler
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.section .text.TIM17_IRQHandler
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.weak TIM17_IRQHandler
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.type TIM17_IRQHandler, %function
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TIM17_IRQHandler:
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b TIM17_IRQHandler
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.section .text.I2C1_IRQHandler
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.weak I2C1_IRQHandler
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.type I2C1_IRQHandler, %function
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I2C1_IRQHandler:
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b I2C1_IRQHandler
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.section .text.SPI1_IRQHandler
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.weak SPI1_IRQHandler
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.type SPI1_IRQHandler, %function
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SPI1_IRQHandler:
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b SPI1_IRQHandler
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.section .text.SPI2_IRQHandler
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.weak SPI2_IRQHandler
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.type SPI2_IRQHandler, %function
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SPI2_IRQHandler:
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b SPI2_IRQHandler
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.section .text.UART1_IRQHandler
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.weak UART1_IRQHandler
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.type UART1_IRQHandler, %function
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UART1_IRQHandler:
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b UART1_IRQHandler
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.section .text.UART2_IRQHandler
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.weak UART2_IRQHandler
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.type UART2_IRQHandler, %function
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UART2_IRQHandler:
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b UART2_IRQHandler
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.section .text.AES_IRQHandler
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.weak AES_IRQHandler
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.type AES_IRQHandler, %function
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AES_IRQHandler:
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b AES_IRQHandler
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.section .text.CAN_IRQHandler
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.weak CAN_IRQHandler
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.type CAN_IRQHandler, %function
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CAN_IRQHandler:
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b CAN_IRQHandler
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.section .text.USB_IRQHandler
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.weak USB_IRQHandler
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.type USB_IRQHandler, %function
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USB_IRQHandler:
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b USB_IRQHandler
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/* ******************** (C) COPYRIGHT 2017 MindMotion ******************** */
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