473 lines
11 KiB
C
473 lines
11 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-10-20 ZYH the first version
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* 2018-04-23 misonyo port to gd32f30x
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* 2019-03-31 xuzhuoyi Porting for gd32e230
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*/
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#include "drv_gpio.h"
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#include <rtdevice.h>
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#include <rthw.h>
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#include "gd32e230.h"
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#include "gd32e230_exti.h"
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#ifdef RT_USING_PIN
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#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \
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GPIO_PIN_##pin, EXTI_SOURCE_GPIO##port, EXTI_SOURCE_PIN##pin}
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#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0}
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/* GD32 GPIO driver */
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struct pin_index
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{
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rt_int16_t index;
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rcu_periph_enum clk;
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rt_uint32_t gpio_periph;
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rt_uint32_t pin;
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rt_uint32_t port_src;
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rt_uint32_t pin_src;
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};
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static const struct pin_index pins[] =
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{
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__GD32_PIN_DEFAULT,
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__GD32_PIN(2, F, 0),
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__GD32_PIN(3, F, 1),
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__GD32_PIN_DEFAULT,
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__GD32_PIN_DEFAULT,
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__GD32_PIN(6, A, 0),
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__GD32_PIN(7, A, 1),
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__GD32_PIN(8, A, 2),
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__GD32_PIN(9, A, 3),
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__GD32_PIN(10, A, 4),
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__GD32_PIN(11, A, 5),
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__GD32_PIN(12, A, 6),
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__GD32_PIN(13, A, 7),
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__GD32_PIN(14, B, 0),
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__GD32_PIN(15, B, 1),
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__GD32_PIN(16, B, 2),
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__GD32_PIN_DEFAULT,
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__GD32_PIN(18, A, 8),
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__GD32_PIN(19, A, 9),
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__GD32_PIN(20, A, 10),
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__GD32_PIN(21, A, 11),
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__GD32_PIN(22, A, 12),
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__GD32_PIN(23, A, 13),
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__GD32_PIN(24, A, 14),
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__GD32_PIN(25, A, 15),
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__GD32_PIN(26, B, 3),
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__GD32_PIN(27, B, 4),
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__GD32_PIN(28, B, 5),
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__GD32_PIN(29, B, 6),
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__GD32_PIN(30, B, 7),
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__GD32_PIN_DEFAULT,
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__GD32_PIN(32, B, 8),
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};
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struct pin_irq_map
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{
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rt_uint16_t pinbit;
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IRQn_Type irqno;
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};
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_PIN_0, EXTI0_1_IRQn},
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{GPIO_PIN_1, EXTI0_1_IRQn},
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{GPIO_PIN_2, EXTI2_3_IRQn},
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{GPIO_PIN_3, EXTI2_3_IRQn},
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{GPIO_PIN_4, EXTI4_15_IRQn},
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{GPIO_PIN_5, EXTI4_15_IRQn},
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{GPIO_PIN_6, EXTI4_15_IRQn},
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{GPIO_PIN_7, EXTI4_15_IRQn},
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{GPIO_PIN_8, EXTI4_15_IRQn},
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{GPIO_PIN_9, EXTI4_15_IRQn},
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{GPIO_PIN_10, EXTI4_15_IRQn},
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{GPIO_PIN_11, EXTI4_15_IRQn},
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{GPIO_PIN_12, EXTI4_15_IRQn},
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{GPIO_PIN_13, EXTI4_15_IRQn},
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{GPIO_PIN_14, EXTI4_15_IRQn},
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{GPIO_PIN_15, EXTI4_15_IRQn},
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};
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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const struct pin_index *get_pin(rt_uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(pins))
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{
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index = &pins[pin];
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if (index->index == -1)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct pin_index *index;
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rt_uint32_t pin_mode;
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rt_uint32_t otype;
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rt_uint32_t pull_up_down;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* GPIO Periph clock enable */
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rcu_periph_clock_enable(index->clk);
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pin_mode = GPIO_MODE_OUTPUT;
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otype = GPIO_OTYPE_PP;
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pull_up_down = GPIO_PUPD_NONE;
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switch(mode)
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{
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case PIN_MODE_OUTPUT:
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/* output setting */
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break;
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case PIN_MODE_OUTPUT_OD:
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/* output setting: od. */
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otype = GPIO_OTYPE_OD;
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break;
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case PIN_MODE_INPUT:
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/* input setting: not pull. */
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pin_mode = GPIO_MODE_INPUT;
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break;
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case PIN_MODE_INPUT_PULLUP:
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/* input setting: pull up. */
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pin_mode = GPIO_MODE_INPUT;
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pull_up_down = GPIO_PUPD_PULLUP;
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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/* input setting: pull down. */
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pin_mode = GPIO_MODE_INPUT;
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pull_up_down = GPIO_PUPD_PULLDOWN;
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break;
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default:
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break;
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}
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gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
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gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin);
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}
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void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
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}
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int gd32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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const struct pin_index *index;
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value = PIN_LOW;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return value;
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}
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value = gpio_input_bit_get(index->gpio_periph, index->pin);
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return value;
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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rt_uint8_t i;
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for (i = 0; i < 32; i++)
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{
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if ((0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t hdr_index = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_EINVAL;
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}
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hdr_index = bit2bitno(index->pin);
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if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[hdr_index].pin == pin &&
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pin_irq_hdr_tab[hdr_index].hdr == hdr &&
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pin_irq_hdr_tab[hdr_index].mode == mode &&
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pin_irq_hdr_tab[hdr_index].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[hdr_index].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EFULL;
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}
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pin_irq_hdr_tab[hdr_index].pin = pin;
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pin_irq_hdr_tab[hdr_index].hdr = hdr;
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pin_irq_hdr_tab[hdr_index].mode = mode;
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pin_irq_hdr_tab[hdr_index].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t hdr_index = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_EINVAL;
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}
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hdr_index = bit2bitno(index->pin);
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if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[hdr_index].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[hdr_index].pin = -1;
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pin_irq_hdr_tab[hdr_index].hdr = RT_NULL;
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pin_irq_hdr_tab[hdr_index].mode = 0;
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pin_irq_hdr_tab[hdr_index].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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{
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const struct pin_index *index;
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t hdr_index = -1;
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exti_trig_type_enum trigger_mode;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return -RT_EINVAL;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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hdr_index = bit2bitno(index->pin);
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if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[hdr_index].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EINVAL;
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}
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irqmap = &pin_irq_map[hdr_index];
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switch (pin_irq_hdr_tab[hdr_index].mode)
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{
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case PIN_IRQ_MODE_RISING:
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trigger_mode = EXTI_TRIG_RISING;
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break;
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case PIN_IRQ_MODE_FALLING:
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trigger_mode = EXTI_TRIG_FALLING;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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trigger_mode = EXTI_TRIG_BOTH;
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break;
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default:
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rt_hw_interrupt_enable(level);
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return -RT_EINVAL;
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}
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//rcu_periph_clock_enable(RCU_AF);
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/* enable and set interrupt priority */
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nvic_irq_enable(irqmap->irqno, 5U);
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/* connect EXTI line to GPIO pin */
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syscfg_exti_line_config(index->port_src, index->pin_src);
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/* configure EXTI line */
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exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
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exti_interrupt_flag_clear((exti_line_enum)(index->pin));
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(index->pin);
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if (irqmap == RT_NULL)
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{
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return -RT_EINVAL;
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}
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nvic_irq_disable(irqmap->irqno);
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}
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else
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{
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return -RT_EINVAL;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _gd32_pin_ops =
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{
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gd32_pin_mode,
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gd32_pin_write,
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gd32_pin_read,
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gd32_pin_attach_irq,
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gd32_pin_detach_irq,
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gd32_pin_irq_enable,
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RT_NULL,
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};
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int rt_hw_pin_init(void)
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{
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int result;
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result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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rt_inline void pin_irq_hdr(int irqno)
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{
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
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{
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if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
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{
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pin_irq_hdr(exti_line);
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exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
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}
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}
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void EXTI0_IRQHandler(void)
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{
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rt_interrupt_enter();
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GD32_GPIO_EXTI_IRQHandler(0);
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rt_interrupt_leave();
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}
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void EXTI1_IRQHandler(void)
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{
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rt_interrupt_enter();
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GD32_GPIO_EXTI_IRQHandler(1);
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rt_interrupt_leave();
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}
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void EXTI2_IRQHandler(void)
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{
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rt_interrupt_enter();
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GD32_GPIO_EXTI_IRQHandler(2);
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rt_interrupt_leave();
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}
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void EXTI3_IRQHandler(void)
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{
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rt_interrupt_enter();
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GD32_GPIO_EXTI_IRQHandler(3);
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rt_interrupt_leave();
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}
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void EXTI4_IRQHandler(void)
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{
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rt_interrupt_enter();
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GD32_GPIO_EXTI_IRQHandler(4);
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rt_interrupt_leave();
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}
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void EXTI5_9_IRQHandler(void)
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{
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rt_interrupt_enter();
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GD32_GPIO_EXTI_IRQHandler(5);
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GD32_GPIO_EXTI_IRQHandler(6);
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GD32_GPIO_EXTI_IRQHandler(7);
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GD32_GPIO_EXTI_IRQHandler(8);
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GD32_GPIO_EXTI_IRQHandler(9);
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rt_interrupt_leave();
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}
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void EXTI10_15_IRQHandler(void)
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{
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rt_interrupt_enter();
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GD32_GPIO_EXTI_IRQHandler(10);
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GD32_GPIO_EXTI_IRQHandler(11);
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GD32_GPIO_EXTI_IRQHandler(12);
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GD32_GPIO_EXTI_IRQHandler(13);
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GD32_GPIO_EXTI_IRQHandler(14);
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GD32_GPIO_EXTI_IRQHandler(15);
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rt_interrupt_leave();
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}
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#endif
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