735 lines
34 KiB
C
735 lines
34 KiB
C
/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_timer6.h
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**
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** A detailed description is available at
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** @link Timer6Group Timer 6 description @endlink
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**
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** - 2018-11-19 CDT First version for Device Driver Library of Timer6.
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**
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******************************************************************************/
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#ifndef __HC32F460_TIMER6_H__
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#define __HC32F460_TIMER6_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_TIMER6_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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*******************************************************************************
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** \defgroup Timer6Group Timer6
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief Timer6 channel enumeration
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******************************************************************************/
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/**
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******************************************************************************
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** \brief Timer6 PWMx port define
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*****************************************************************************/
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typedef enum en_timer6_chx_port
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{
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Timer6PWMA = 0u, ///< PWM A port
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Timer6PWMB = 1u, ///< PWM B port
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}en_timer6_chx_port_t;
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/**
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******************************************************************************
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** \brief Timer6 TRIG port define
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*****************************************************************************/
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typedef enum en_timer6_input_port
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{
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Timer6xCHA = 0u, ///< PWM A port
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Timer6xCHB = 1u, ///< PWM B port
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Timer6TrigA = 2u, ///< Timer6x trigger A port
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Timer6TrigB = 3u, ///< Timer6x trigger B port
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}en_timer6_input_port_t;
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/**
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******************************************************************************
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** \brief Timer6 general control - Z Phase input mask periods
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_gconr_zmsk
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{
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Timer6ZMaskDis = 0u, ///< Z Phase input mask disable
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Timer6ZMask4Cyl = 1u, ///< Mask Z phase input during 4 periods when over fllow or under fllow of position count
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Timer6ZMask8Cyl = 2u, ///< Mask Z phase input during 8 periods when over fllow or under fllow of position count
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Tiemr6ZMask16Cyl = 3u, ///< Mask Z phase input during 16 periods when over fllow or under fllow of position count
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}en_timer6_gconr_zmsk_t;
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/**
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*******************************************************************************
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** \brief Clock division enumeration
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******************************************************************************/
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typedef enum en_timer6_clk_div
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{
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Timer6PclkDiv1 = 0u, ///< Count clock: pclk
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Timer6PclkDiv2 = 1u, ///< Count clock: pclk/2
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Timer6PclkDiv4 = 2u, ///< Count clock: pclk/4
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Timer6PclkDiv8 = 3u, ///< Count clock: pclk/8
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Timer6PclkDiv16 = 4u, ///< Count clock: pclk/16
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Timer6PclkDiv64 = 5u, ///< Count clock: pclk/64
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Timer6PclkDiv256 = 6u, ///< Count clock: pclk/256
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Timer6PclkDiv1024 = 7u, ///< Count clock: pclk/1024
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} en_timer6_clk_div_t;
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/**
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*******************************************************************************
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** \brief Count mode enumeration
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******************************************************************************/
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typedef enum en_timer6_count_mode
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{
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Timer6CntSawtoothMode = 0u, ///< Sawtooth wave mode
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Timer6CntTriangularModeA = 4u, ///< Triangular wave mode
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Timer6CntTriangularModeB = 5u, ///< Triangular wave mode
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} en_timer6_count_mode_t;
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/**
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*******************************************************************************
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** \brief Count direction enumeration
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******************************************************************************/
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typedef enum en_timer6_count_dir
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{
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Timer6CntDirDown = 0u, ///< Counter counting up
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Timer6CntDirUp = 1u, ///< Counter counting down
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} en_timer6_count_dir_t;
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/**
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******************************************************************************
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** \brief Timer6 period register
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_period
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{
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Timer6PeriodA = 0u, ///< Period Register A
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Timer6PeriodB = 1u, ///< Period Register B
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Timer6PeriodC = 2u, ///< Period Register C
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}en_timer6_period_t;
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/**
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******************************************************************************
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** \brief Timer6 general compare match register
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_compare
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{
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Timer6GenCompareA = 0u, ///< General Compare Match A Register
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Timer6GenCompareB = 1u, ///< General Compare Match B Register
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Timer6GenCompareC = 2u, ///< General Compare Match C Register
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Timer6GenCompareD = 3u, ///< General Compare Match D Register
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Timer6GenCompareE = 4u, ///< General Compare Match E Register
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Timer6GenCompareF = 5u, ///< General Compare Match F Register
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}en_timer6_compare_t;
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/**
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******************************************************************************
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** \brief Timer6 special compare match register
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_special_compare
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{
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Timer6SpclCompA = 0u, ///< Special Compare Match A Register
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Timer6SpclCompB = 1u, ///< Special Compare Match B Register
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Timer6SpclCompC = 2u, ///< Special Compare Match C Register
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Timer6SpclCompD = 3u, ///< Special Compare Match D Register
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Timer6SpclCompE = 4u, ///< Special Compare Match E Register
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Timer6SpclCompF = 5u, ///< Special Compare Match F Register
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}en_timer6_special_compare_t;
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/**
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******************************************************************************
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** \brief Timer6 dead timer value register
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_dead_time_reg
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{
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Timer6DeadTimUpAR = 0u, ///< Dead timer for up count A Register
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Timer6DeadTimUpBR = 1u, ///< Dead timer for up count B Register
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Timer6DeadTimDwnAR = 2u, ///< Dead timer for down count A Register
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Timer6DeadTimDwnBR = 3u, ///< Dead timer for down count B Register
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}en_timer6_dead_time_reg_t;
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/**
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******************************************************************************
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** \brief Timer6 port control - port output control of brake status
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_pconr_disval
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{
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Timer6PWMxDisValNorm = 0u, ///< PWMx port output normal when brake
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Timer6PWMxDisValHiZ = 1u, ///< PWMx port Hi-z when brake
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Timer6PWMxDisValLow = 2u, ///< PWMx port output low level when brake
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Timer6PWMxDisValHigh = 3u, ///< PWMx port output high level when brake
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}en_timer6_pconr_disval_t;
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/**
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******************************************************************************
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** \brief Timer6 port - PWMx port output status when CNTER value match GCMxR or PERAR
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_pconr_cmpc
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{
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Timer6PWMxCompareLow = 0u, ///< PWMx port output Low level when CNTER value match with GCMxR or PERAR
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Timer6PWMxCompareHigh = 1u, ///< PWMx port output high level when CNTER value match with GCMxR or PERAR
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Timer6PWMxCompareKeep = 2u, ///< PWMx port output keep former level when CNTER value match GCMxR or PERAR
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Timer6PWMxCompareInv = 3u, ///< PWMx port output inverse level when CNTER value match with GCMxR or PERAR
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}en_timer6_pconr_cmpc_t;
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/**
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******************************************************************************
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** \brief Timer6 port- PWMx port output set(STA STP)
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_pconr_port_out
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{
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Timer6PWMxPortOutLow = 0u, ///< PWMx port output set low level
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Timer6PWMxPortOutHigh = 1u, ///< PWMx port output set high level
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}en_timer6_pconr_port_out_t;
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/**
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*******************************************************************************
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** \brief Timer6 function mode selection enumeration
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******************************************************************************/
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typedef enum en_timer6_func_mode
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{
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Timer6ModeCompareOutput = 0u, ///< Compare output function
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Timer6ModeCaptureInput = 1u, ///< Capture input function
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} en_timer6_func_mode_t;
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/**
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******************************************************************************
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** \brief Timer6 port - PWMx STA STP function selection
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_pconr_stastps
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{
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Timer6PWMxStateSelSS = 0u, ///< PWMx output status is decide by STACx STPCx when CNTER start and stop
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Timer6PWMxStateSelKeep = 1u, ///< PWMx output status keep former level when CNTER start and stop
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}en_timer6_pconr_stastps_t;
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/**
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******************************************************************************
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** \brief Timer6 buffer - General compare register / Period register transfer function selection
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**
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** \note
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** For General compare register:
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** Single buffer stransfer: Compare Ouput: GCMCR-->GCMAR / GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR / GCMDR-->GCMBR
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** Double buffer stransfer: Compare Ouput: GCMER-->GCMCR-->GCMAR / GCMFR-->GCMDR-->GCMBR Capture Input: GCMAR-->GCMCR-->GCMER /GCMFR-->GCMDR-->GCMBR
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** For Period register:
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** Single buffer stransfer: PERBR-->PERAR
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** Double buffer stransfer: PERCR-->PERBR-->PERAR
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******************************************************************************/
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typedef enum en_timer6_buf_gcmp_prd
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{
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Timer6GcmpPrdSingleBuf = 0u, ///< Single buffer stransfer
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Timer6GcmpPrdDoubleBuf = 1u, ///< Double buffer stransfer
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}en_timer6_buf_gcmp_prd_t;
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/**
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******************************************************************************
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** \brief Timer6 buffer - Special compare register transfer function selection
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_buf_spcl_cmp
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{
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Timer6SpclSingleBuf = 0u, ///< Single buffer stransfer: Compare Ouput: SCMCR-->SCMAR / SCMDR-->SCMBR
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Timer6SpclDoubleBuf = 1u, ///< Double buffer stransfer: Compare Ouput: SCMER-->SCMCR-->SCMAR / SCMFR-->SCMDR-->SCMBR
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}en_timer6_buf_spcl_cmp_t;
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/**
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******************************************************************************
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** \brief Timer6 buffer - Special compare register transfer opportunity selection
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_buf_spcl_opt
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{
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Timer6SplcOptNone = 0u, ///< No transfer
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Timer6SplcOptOverFlow = 1u, ///< Transfer when over flow (About sawtooth mode,accord to the count direction)
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Timer6SplcOptUnderFlow = 2u, ///< Transfer when under flow (About sawtooth mode,accord to the count direction)
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Timer6SplcOptBoth = 3u, ///< Transfer when over flow or under flow (About sawtooth mode,accord to the count direction)
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}en_timer6_buf_spcl_opt_t;
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/**
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******************************************************************************
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** \brief ADT dead timer control - PWMx dead timer separate set
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_dconr_sepa
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{
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Timer6PWMxDtSeparate = 0u, ///< The dead timer of up count and down count separate set by DTUAR and DTDAR
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Timer6PWMxDtEqual = 1u, ///< the values of DTUAR and DTDAR are equal automatically
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}en_timer6_dconr_sepa_t;
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/**
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******************************************************************************
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** \brief ADT filter control- TRIx/PWMx port filter sample clock selection
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_fconr_fltclk
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{
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Timer6FltClkPclk0Div1 = 0u, ///< PCLK0
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Timer6FltClkPclk0Div4 = 1u, ///< PCLK0/4
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Timer6FltClkPclk0Div16 = 2u, ///< PCLK0/16
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Timer6FltClkPclk0Div64 = 3u, ///< PCLK0/64
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}en_timer6_fconr_fltclk_t;
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/**
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******************************************************************************
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** \brief Timer6 valid period repeat- TIMx valid period repeat function selection(trigger interrupt or AOS event)
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_vperr_pcnts
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{
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Timer6PeriodCnts0 = 0u, ///< Valid period repeat function disable
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Timer6PeriodCnts1 = 1u, ///< Enable every other one period
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Timer6PeriodCnts2 = 2u, ///< Enable every other two periods
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Timer6PeriodCnts3 = 3u, ///< Enable every other three periods
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Timer6PeriodCnts4 = 4u, ///< Enable every other four periods
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Timer6PeriodCnts5 = 5u, ///< Enable every other five periods
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Timer6PeriodCnts6 = 6u, ///< Enable every other six periods
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Timer6PeriodCnts7 = 7u, ///< Enable every other seven periods
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}en_timer6_vperr_pcnts_t;
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/**
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******************************************************************************
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** \brief Timer6 valid period repeat- Count condition select
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_vperr_pcnte
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{
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Timer6PeriodCnteDisable = 0u, ///< Valid period repeat function disable
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Timer6PeriodCnteMin = 1u, ///< Over flow and under flow point of Sawtooth wave mode, or under flow point of Triangular wave mode
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Timer6PeriodCnteMax = 2u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow point of Triangular wave mode
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Timer6PeriodCnteBoth = 3u, ///< Over flow and under flow point of Sawtooth wave mode, or voer flow and under flow point of Triangular wave mode
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}en_timer6_vperr_pcnte_t;
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/**
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******************************************************************************
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** \brief Timer6 Hardware(Start/Stop/Clear/Capture) event trigger select
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_hw_trig
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{
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Timer6HwTrigAos0 = 0u, ///< Hardware trigger event from AOS0(HTSSR0)
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Timer6HwTrigAos1 = 1u, ///< Hardware trigger event from AOS1(HTSSR1)
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Timer6HwTrigPWMARise = 4u, ///< Hardware trigger event from PWMA rising
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Timer6HwTrigPWMAFall = 5u, ///< Hardware trigger event from PWMA falling
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Timer6HwTrigPWMBRise = 6u, ///< Hardware trigger event from PWMA rising
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Timer6HwTrigPWMBFall = 7u, ///< Hardware trigger event from PWMA falling
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Timer6HwTrigTimTriARise = 8u, ///< Hardware trigger event from TRIGA rising
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Timer6HwTrigTimTriAFall = 9u, ///< Hardware trigger event from TRIGA falling
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Timer6HwTrigTimTriBRise = 10u, ///< Hardware trigger event from TRIGB rising
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Timer6HwTrigTimTriBFall = 11u, ///< Hardware trigger event from TRIGB falling
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Timer6HwTrigEnd = 16u,
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}en_timer6_hw_trig_t;
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/**
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******************************************************************************
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** \brief Timer6 hardware (up count/down count) event trigger select
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_hw_cnt
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{
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Timer6HwCntPWMALowPWMBRise = 0u, ///< PWMB Rising trigger when PWMA is low level
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Timer6HwCntPWMALowPWMBFall = 1u, ///< PWMB falling trigger when PWMA is low level
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Timer6HwCntPWMAHighPWMBRise = 2u, ///< PWMB Rising trigger when PWMA is high level
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Timer6HwCntPWMAHighPWMBFall = 3u, ///< PWMB falling trigger when PWMA is high level
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Timer6HwCntPWMBLowPWMARise = 4u, ///< PWMA Rising trigger when PWMB is low level
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Timer6HwCntPWMBLowPWMAFall = 5u, ///< PWMA falling trigger when PWMB is low level
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Timer6HwCntPWMBHighPWMARise = 6u, ///< PWMA Rising trigger when PWMB is high level
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Timer6HwCntPWMBHighPWMAFall = 7u, ///< PWMA falling trigger when PWMB is high level
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Timer6HwCntTRIGARise = 8u, ///< TRIGA rising trigger
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Timer6HwCntTRIGAFall = 9u, ///< TRIGA falling trigger
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Timer6HwCntTRIGBRise = 10u, ///< TRIGB rising trigger
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Timer6HwCntTRIGBFall = 11u, ///< TRIGB falling trigger
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Timer6HwCntAos0 = 16u, ///< AOS0 trigger
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Timer6HwCntAos1 = 17u, ///< AOS1 trigger
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Timer6HwCntMax = 18u,
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}en_timer6_hw_cnt_t;
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/**
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******************************************************************************
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** \brief Timer6 interrupt type
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_irq_type
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{
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Timer6INTENA = 0u, ///< Interrupt of count equal to GCMA (or capture input A)
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Timer6INTENB = 1u, ///< Interrupt of count equal to GCMB (or capture input B)
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Timer6INTENC = 2u, ///< Interrupt of count equal to GCMC
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Timer6INTEND = 3u, ///< Interrupt of count equal to GCMD
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Timer6INTENE = 4u, ///< Interrupt of count equal to GCME
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Timer6INTENF = 5u, ///< Interrupt of count equal to GCMF
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Timer6INTENOVF = 6u, ///< Interrupt of over flow of sawtooth wave mode or peak point of triangular wave mode
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Timer6INTENUDF = 7u, ///< Interrupt of under flow of sawtooth wave mode or valley point of triangular wave mode
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Timer6INTENDTE = 8u, ///< Interrupt of dead timer error
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Timer6INTENSAU = 16u, ///< Interrupt of count up equally compared with SCMA
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Timer6INTENSAD = 17u, ///< Interrupt of count down equally compared with SCMA
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Timer6INTENSBU = 18u, ///< Interrupt of count up equally compared with SCMB
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Timer6INTENSBD = 19u, ///< Interrupt of count down equally compared with SCMB
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}en_timer6_irq_type_t;
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/**
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******************************************************************************
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** \brief Timer6 status flag
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**
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** \note
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******************************************************************************/
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typedef enum en_timer6_status
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{
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Timer6CMAF = 0u, ///< Status flag of count equal to GCMA (or capture input A)
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Timer6CMBF = 1u, ///< Status flag of count equal to GCMB (or capture input B)
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Timer6CMCF = 2u, ///< Status flag of count equal to GCMC
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Timer6CMDF = 3u, ///< Status flag of count equal to GCMD
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Timer6CMEF = 4u, ///< Status flag of count equal to GCME
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Timer6CMFF = 5u, ///< Status flag of count equal to GCMF
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Timer6OVFF = 6u, ///< Status flag of over flow of sawtooth wave mode or peak point of triangular wave mode
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Timer6UDFF = 7u, ///< Status flag of under flow of sawtooth wave mode or valley point of triangular wave mode
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Timer6DTEF = 8u, ///< Status flag of dead timer error
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Timer6CMSAUF = 9u, ///< Status flag of count up equally compared with SCMA
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Timer6CMSADF = 10u, ///< Status flag of count down equally compared with SCMA
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Timer6CMSBUF = 11u, ///< Status flag of count up equally compared with SCMB
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Timer6CMSBDF = 12u, ///< Status flag of count down equally compared with SCMB
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Timer6VPERNUM = 21, ///< Number of valid period
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Timer6DIRF = 31, ///< Count direction
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}en_timer6_status_t;
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/**
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*******************************************************************************
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** \brief Timer6 common trigger source select enumeration
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**
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******************************************************************************/
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typedef enum en_timer6_com_trigger
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{
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Timer6ComTrigger_1 = 1u, ///< Select common trigger 1.
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Timer6ComTrigger_2 = 2u, ///< Select common trigger 2.
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Timer6ComTrigger_1_2 = 3u, ///< Select common trigger 1 and 2.
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} en_timer6_com_trigger_t;
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/**
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******************************************************************************
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** \brief Timer6 software synchronous config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_sw_sync
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{
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bool bTimer61; ///< Timer6 unit1
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bool bTimer62; ///< Timer6 unit2
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bool bTimer63; ///< Timer6 unit3
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}stc_timer6_sw_sync_t;
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/**
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******************************************************************************
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** \brief Timer6 base init structure definition
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** \note
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******************************************************************************/
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typedef struct stc_timer6_basecnt_cfg
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{
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en_timer6_count_mode_t enCntMode; ///< Count mode
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en_timer6_count_dir_t enCntDir; ///< Count direction
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en_timer6_clk_div_t enCntClkDiv; ///< Count clock division select
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}stc_timer6_basecnt_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 Trig port config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_port_trig_cfg
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{
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bool bFltEn; ///< trig source capture input filter enable
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en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock
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}stc_tiemr6_port_trig_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 port output config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_port_output_cfg
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{
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en_timer6_func_mode_t enPortMode; ///< Port mode
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bool bOutEn; ///< Output enable / disable
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en_timer6_pconr_cmpc_t enPerc; ///< Port state when counter match the period
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en_timer6_pconr_cmpc_t enCmpc; ///< Port state when counter match GCMAR(GCMBR)
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en_timer6_pconr_stastps_t enStaStp; ///< Post state selection when count start/stop
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en_timer6_pconr_port_out_t enStaOut; ///< Port state when count start
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en_timer6_pconr_port_out_t enStpOut; ///< port stop when count stop
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en_timer6_pconr_disval_t enDisVal; ///< Port output state when brake
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}stc_timer6_port_output_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 port input config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_port_input_cfg
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{
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en_timer6_input_port_t enPortSel; ///< Port select
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en_timer6_func_mode_t enPortMode; ///< Port mode
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bool bFltEn; ///< trig source capture input filter enable
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en_timer6_fconr_fltclk_t enFltClk; ///< Filter clock
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}stc_timer6_port_input_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 hardware dead time function config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_deadtime_cfg
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{
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bool bEnDeadtime; ///< Enable hardware dead time function
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bool bEnDtBufUp; ///< Enable buffer transfer for up count dead time register(DTUBR-->DTUAR)
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bool bEnDtBufDwn; ///< Enable buffer transfer for down count dead time register(DTDBR-->DTDAR)
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bool bEnDtEqualUpDwn; ///< Enable down count dead time register equal to up count DT register
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}stc_timer6_deadtime_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 valid period config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_validper_cfg
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{
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en_timer6_vperr_pcnts_t enValidCntNum; ///< Valid period selection
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en_timer6_vperr_pcnte_t enValidCdtEn; ///< Count condition of valid period
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bool bPeriodSCMA; ///< Sepcial signal A valid period selection enable
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bool bPeriodSCMB; ///< Sepcial signal A valid period selection enable
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}stc_timer6_validper_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 general compare register buffer transfer config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_gcmp_buf_cfg
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{
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bool bEnGcmpTransBuf; ///< Enable/Disable buffer transfer
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en_timer6_buf_gcmp_prd_t enGcmpBufTransType; ///< Sigle or double buffer transfer
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}stc_timer6_gcmp_buf_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 period register buffer transfer config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_period_buf_cfg
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{
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bool bEnPeriodTransBuf; ///< Enable/Disable buffer transfer
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en_timer6_buf_gcmp_prd_t enPeriodBufTransType; ///< Sigle or double buffer transfer
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}stc_timer6_period_buf_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 Specila compare register buffer transfer config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_spcl_buf_cfg
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{
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bool bEnSpclTransBuf; ///< Enable/Disable buffer transfer
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en_timer6_buf_spcl_cmp_t enSpclBufTransType; ///< Sigle or double buffer transfer
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en_timer6_buf_spcl_opt_t enSpclBufOptType; ///< Buffer transfer opportunity
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}stc_timer6_spcl_buf_cfg_t;
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/**
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******************************************************************************
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** \brief Timer6 Z phase input mask config
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** \note
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******************************************************************************/
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typedef struct stc_timer6_zmask_cfg
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{
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en_timer6_gconr_zmsk_t enZMaskCycle; ///< Z phase input mask periods selection
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bool bFltPosCntMaksEn; ///< As position count timer, position counter clear function enable(TRUE) or disable(FALSE) during the time of Z phase input mask
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bool bFltRevCntMaksEn; ///< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) during the time of Z phase input mask
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}stc_timer6_zmask_cfg_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/* IRQ config */
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en_result_t Timer6_ConfigIrq(M4_TMR6_TypeDef *TMR6x, en_timer6_irq_type_t enTimer6Irq, bool bEn);
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/* Get status(flag) */
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uint8_t Timer6_GetStatus(M4_TMR6_TypeDef *TMR6x, en_timer6_status_t enStatus);
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/* Base functions */
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en_result_t Timer6_DeInit(M4_TMR6_TypeDef *TMR6x);
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en_result_t Timer6_Init(M4_TMR6_TypeDef *TMR6x, const stc_timer6_basecnt_cfg_t* pstcTimer6BaseCntCfg);
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/* Timer6 unit start count*/
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en_result_t Timer6_StartCount(M4_TMR6_TypeDef *TMR6x);
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/* Timer6 unit stop count*/
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en_result_t Timer6_StopCount(M4_TMR6_TypeDef *TMR6x);
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/* Timer6 unit Set Count Value*/
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en_result_t Timer6_SetCount(M4_TMR6_TypeDef *TMR6x, uint16_t u16Value);
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/* Timer6 unit Get Count Value*/
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uint16_t Timer6_GetCount(M4_TMR6_TypeDef *TMR6x);
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/* Timer6 unit Clear Count Value*/
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en_result_t Timer6_ClearCount(M4_TMR6_TypeDef *TMR6x);
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/* Timer6 unit Set Period and buffer Value*/
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en_result_t Timer6_SetPeriod(M4_TMR6_TypeDef *TMR6x, en_timer6_period_t enTimer6Periodx, uint16_t u16Period);
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/* Timer6 unit set general compare register value*/
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en_result_t Timer6_SetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare, uint16_t u16Compare);
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/* Timer6 unit set specoal compare register value*/
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en_result_t Timer6_SetSpecialCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_special_compare_t enTimer6SpclCmp, uint16_t u16SpclCmp);
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/* Timer6 unit get general compare register value*/
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uint16_t Timer6_GetGeneralCmpValue(M4_TMR6_TypeDef *TMR6x, en_timer6_compare_t enTimer6Compare);
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/* Timer6 unit set period buffer transfer function*/
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en_result_t Timer6_SetPeriodBuf(M4_TMR6_TypeDef *TMR6x, const stc_timer6_period_buf_cfg_t* pstcTimer6PrdBufCfg);
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/* Timer6 unit set general compare buffer transfer function*/
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en_result_t Timer6_SetGeneralBuf(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_gcmp_buf_cfg_t* pstcTimer6GenBufCfg);
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/* Timer6 unit set special compare buffer transfer function*/
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en_result_t Timer6_SetSpecialBuf(M4_TMR6_TypeDef *TMR6x,en_timer6_special_compare_t enTimer6SpclCmp, const stc_timer6_spcl_buf_cfg_t* pstcTimer6SpclBufCfg);
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/* Timer6 unit Set valid period Value*/
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en_result_t Timer6_SetValidPeriod(M4_TMR6_TypeDef *TMR6x, const stc_timer6_validper_cfg_t* pstcTimer6ValidPerCfg);
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/* Config Input prot and filter function */
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en_result_t Timer6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, const stc_timer6_port_input_cfg_t* pstcTimer6PortInputCfg);
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/* Config output prot function */
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en_result_t Timer6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, en_timer6_chx_port_t enTimer6PWMPort, const stc_timer6_port_output_cfg_t* pstcTimer6PortOutCfg);
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/* Set dead time register value */
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en_result_t Timer6_SetDeadTimeValue(M4_TMR6_TypeDef *TMR6x, en_timer6_dead_time_reg_t enTimer6DTReg, uint16_t u16DTValue);
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/* Config dead time function */
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en_result_t Timer6_ConfigDeadTime(M4_TMR6_TypeDef *TMR6x, const stc_timer6_deadtime_cfg_t* pstcTimer6DTCfg);
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/* Config Software Synchrony Stop */
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en_result_t Timer6_SwSyncStart(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStart);
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/* Config Software Synchrony Start */
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en_result_t Timer6_SwSyncStop(const stc_timer6_sw_sync_t* pstcTimer6SwSyncStop);
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/* Config Software Synchrony Clear */
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en_result_t Timer6_SwSyncClear(const stc_timer6_sw_sync_t* pstcTimer6SwSyncClear);
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/* Get Software Synchrony Status */
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en_result_t Timer6_GetSwSyncState(stc_timer6_sw_sync_t* pstcTimer6SwSyncState);
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/* Config Hardware up count event */
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en_result_t Timer6_ConfigHwCntUp(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntUp);
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/* Clear Hardware up count event */
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en_result_t Timer6_ClearHwCntUp(M4_TMR6_TypeDef *TMR6x);
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/* Config Hardware down count event */
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en_result_t Timer6_ConfigHwCntDwn(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_cnt_t enTimer6HwCntDwn);
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/* Clear Hardware down count event */
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en_result_t Timer6_ClearHwCntDwn(M4_TMR6_TypeDef *TMR6x);
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/* Config Hardware start event */
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en_result_t Timer6_ConfigHwStart(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStart);
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/* Clear Hardware start event */
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en_result_t Timer6_ClearHwStart(M4_TMR6_TypeDef *TMR6x);
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/* Enable Hardware start event */
|
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en_result_t Timer6_EnableHwStart(M4_TMR6_TypeDef *TMR6x);
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/* Dsiable Hardware start event */
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en_result_t Timer6_DisableHwStart(M4_TMR6_TypeDef *TMR6x);
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|
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/* Config Hardware stop event */
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en_result_t Timer6_ConfigHwStop(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwStop);
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/* Clear Hardware stop event */
|
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en_result_t Timer6_ClearHwStop(M4_TMR6_TypeDef *TMR6x);
|
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/* Enable Hardware stop event */
|
|
en_result_t Timer6_EnableHwStop(M4_TMR6_TypeDef *TMR6x);
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/* Disable Hardware stop event */
|
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en_result_t Timer6_DisableHwStop(M4_TMR6_TypeDef *TMR6x);
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|
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/* Config Hardware clear event */
|
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en_result_t Timer6_ConfigHwClear(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwClear);
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/* Clear Hardware clear event */
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en_result_t Timer6_ClearHwClear(M4_TMR6_TypeDef *TMR6x);
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/* Enable Hardware clear event */
|
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en_result_t Timer6_EnableHwClear(M4_TMR6_TypeDef *TMR6x);
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/* Dsiable Hardware clear event */
|
|
en_result_t Timer6_DisableHwClear(M4_TMR6_TypeDef *TMR6x);
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|
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/* Config Hardware capture event A */
|
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en_result_t Timer6_ConfigHwCaptureA(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureA);
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/* Clear Hardware capture event A */
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en_result_t Timer6_ClearHwCaptureA(M4_TMR6_TypeDef *TMR6x);
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/* Config Hardware capture event B */
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en_result_t Timer6_ConfigHwCaptureB(M4_TMR6_TypeDef *TMR6x, en_timer6_hw_trig_t enTimer6HwCaptureB);
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/* Clear Hardware capture event B */
|
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en_result_t Timer6_ClearHwCaptureB(M4_TMR6_TypeDef *TMR6x);
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|
|
|
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/* Set trigger source 0 of hardware event */
|
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en_result_t Timer6_SetTriggerSrc0(en_event_src_t enTriggerSrc);
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/* Set trigger source 1 of hardware event */
|
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en_result_t Timer6_SetTriggerSrc1(en_event_src_t enTriggerSrc);
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/* Enable or disable Timer6 common trigger for Hardware trigger source 0 */
|
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void TIMER6_ComTriggerCmd0(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState);
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/* Enable or disable Timer6 common trigger for Hardware trigger source 1 */
|
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void TIMER6_ComTriggerCmd1(en_timer6_com_trigger_t enComTrigger, en_functional_state_t enState);
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|
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/* Z phase input mask config */
|
|
en_result_t Timer6_ConfigZMask(M4_TMR6_TypeDef *TMR6x, const stc_timer6_zmask_cfg_t* pstcTimer6ZMaskCfg);
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|
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//@} // Timer6Group
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|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
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|
|
#endif /* DDL_TIMER6_ENABLE */
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|
|
|
#endif /* __HC32F460_TIMER6_H__ */
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|
|
/*******************************************************************************
|
|
* EOF (not truncated)
|
|
******************************************************************************/
|