510 lines
23 KiB
C
510 lines
23 KiB
C
/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_adc.h
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**
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** A detailed description is available at
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** @link AdcGroup Adc description @endlink
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**
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** - 2018-11-30 CDT First version for Device Driver Library of Adc.
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**
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******************************************************************************/
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#ifndef __HC32F460_ADC_H__
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#define __HC32F460_ADC_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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#if (DDL_ADC_ENABLE == DDL_ON)
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup AdcGroup Analog-to-Digital Converter(ADC)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief ADC average count.
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**
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******************************************************************************/
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typedef enum en_adc_avcnt
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{
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AdcAvcnt_2 = 0x0, ///< Average after 2 conversions.
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AdcAvcnt_4 = 0x1, ///< Average after 4 conversions.
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AdcAvcnt_8 = 0x2, ///< Average after 8 conversions.
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AdcAvcnt_16 = 0x3, ///< Average after 16 conversions.
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AdcAvcnt_32 = 0x4, ///< Average after 32 conversions.
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AdcAvcnt_64 = 0x5, ///< Average after 64 conversions.
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AdcAvcnt_128 = 0x6, ///< Average after 128 conversions.
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AdcAvcnt_256 = 0x7, ///< Average after 256 conversions.
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} en_adc_avcnt_t;
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/**
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*******************************************************************************
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** \brief ADC data alignment
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**
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******************************************************************************/
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typedef enum en_adc_data_align
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{
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AdcDataAlign_Right = 0x0, ///< Data right alignment.
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AdcDataAlign_Left = 0x1, ///< Data left alignment.
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} en_adc_data_align_t;
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/**
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*******************************************************************************
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** \brief Automatically clear data registers after reading data.
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** The auto clear function is mainly used to detect whether the data register
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** is updated.
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**
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******************************************************************************/
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typedef enum en_adc_clren
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{
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AdcClren_Disable = 0x0, ///< Automatic clear function disable.
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AdcClren_Enable = 0x1, ///< Automatic clear function enable.
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} en_adc_clren_t;
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/**
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*******************************************************************************
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** \brief ADC resolution.
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**
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******************************************************************************/
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typedef enum en_adc_resolution
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{
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AdcResolution_12Bit = 0x0, ///< Resolution is 12 bit.
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AdcResolution_10Bit = 0x1, ///< Resolution is 10 bit.
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AdcResolution_8Bit = 0x2, ///< Resolution is 8 bit.
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} en_adc_resolution_t;
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/**
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*******************************************************************************
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** \brief ADC scan mode.
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**
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******************************************************************************/
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typedef enum en_adc_scan_mode
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{
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AdcMode_SAOnce = 0x0, ///< Sequence A works once.
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AdcMode_SAContinuous = 0x1, ///< Sequence A works always.
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AdcMode_SAOnceSBOnce = 0x2, ///< Sequence A and sequence B work once.
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AdcMode_SAContinuousSBOnce = 0x3, ///< Sequence A works always, sequence works once.
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} en_adc_scan_mode_t;
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/**
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*******************************************************************************
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** \brief ADC sequence A restart position.
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**
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******************************************************************************/
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typedef enum en_adc_rschsel
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{
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AdcRschsel_Continue = 0x0, ///< After sequence A is interrupted by sequence B,
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///< sequence A continues to scan from the interrupt
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///< when it restarts.
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AdcRschsel_Restart = 0x1, ///< After sequence A is interrupted by sequence B,
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///< sequence A restarts scanning from the first channel
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///< when it restarts.
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} en_adc_rschsel_t;
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/**
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*******************************************************************************
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** \brief ADC external or internal trigger source enable/disable .
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**
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******************************************************************************/
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typedef enum en_adc_trgen
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{
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AdcTrgen_Disable = 0x0, ///< External or internal trigger source disable.
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AdcTrgen_Enable = 0x1, ///< External or internal trigger source enable.
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} en_adc_trgen_t;
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/**
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*******************************************************************************
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** \brief ADC sequence trigger source selection.
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**
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******************************************************************************/
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typedef enum en_adc_trgsel
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{
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AdcTrgsel_ADTRGX = 0x0, ///< X = 1(use ADC1) / 2(use ADC2), same as below.
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AdcTrgsel_TRGX0 = 0x1, ///< Pin IN_TRG10 / IN_TRG20.
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AdcTrgsel_TRGX1 = 0x2, ///< Pin IN_TRG11 / IN_TRG21.
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AdcTrgsel_TRGX0_TRGX1 = 0x3, ///< Pin IN_TRG10 + IN_TRG11 / IN_TRG20 + IN_TRG21.
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} en_adc_trgsel_t;
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/**
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*******************************************************************************
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** \brief Sequence A/B conversion completion interrupt enable/disable.
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**
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******************************************************************************/
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typedef enum en_adc_eocien
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{
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AdcEocien_Disable = 0x0, ///< Conversion completion interrupt disable.
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AdcEocien_Enable = 0x1, ///< Conversion completion interrupt enable.
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} en_adc_eocien_t;
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/**
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*******************************************************************************
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** \brief ADC sync mode.
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**
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******************************************************************************/
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typedef enum en_adc_sync_mode
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{
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AdcSync_SingleSerial = 0x0u, ///< Single: ADC1 and ADC2 only sample and convert once after triggering.
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///< Serial: ADC2 start after ADC1 N PCLK4 cycles.
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AdcSync_SingleParallel = 0x2u, ///< Parallel: ADC1 and ADC2 start at the same time.
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AdcSync_ContinuousSerial = 0x4u, ///< Continuous: ADC1 and ADC2 continuously sample and convert after triggering.
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AdcSync_ContinuousParallel = 0x6u,
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} en_adc_sync_mode_t;
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/**
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*******************************************************************************
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** \brief ADC sync enable/disable.
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**
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******************************************************************************/
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typedef enum en_adc_syncen
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{
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AdcSync_Disable = 0x0, ///< Disable sync mode.
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AdcSync_Enable = 0x1, ///< Enable sync mode.
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} en_adc_syncen_t;
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/**
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*******************************************************************************
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** \brief Analog watchdog interrupt enable/disable.
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**
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******************************************************************************/
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typedef enum en_adc_awdien
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{
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AdcAwdInt_Disable = 0x0, ///< Disable AWD interrupt.
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AdcAwdInt_Enable = 0x1, ///< Enable AWD interrupt.
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} en_adc_awdien_t;
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/**
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*******************************************************************************
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** \brief Analog watchdog interrupt event sequence selection.
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**
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******************************************************************************/
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typedef enum en_adc_awdss
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{
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AdcAwdSel_SA_SB = 0x0, ///< Sequence A and B output interrupt event -- ADC_SEQCMP.
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AdcAwdSel_SA = 0x1, ///< Sequence A output interrupt event -- ADC_SEQCMP.
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AdcAwdSel_SB = 0x2, ///< Sequence B output interrupt event -- ADC_SEQCMP.
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AdcAwdSel_SB_SA = 0x3, ///< Same as AdcAwdSel_SA_SB.
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} en_adc_awdss_t;
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/**
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*******************************************************************************
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** \brief Analog watchdog comparison mode selection.
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**
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******************************************************************************/
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typedef enum en_adc_awdmd
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{
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AdcAwdCmpMode_0 = 0x0, ///< Upper limit is AWDDR0, lower limit is AWDDR1.
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///< If AWDDR0 > result or result > AWDDR1,
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///< the interrupt will be occur.
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AdcAwdCmpMode_1 = 0x1, ///< The range is [AWDDR0, AWDDR1].
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///< If AWDDR0 <= result <= AWDDR1, the interrupt will be occur.
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} en_adc_awdmd_t;
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/**
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*******************************************************************************
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** \brief Analog watchdog enable/disable.
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**
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******************************************************************************/
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typedef enum en_adc_awden
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{
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AdcAwd_Disable = 0x0, ///< Disable AWD.
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AdcAwd_Enable = 0x1, ///< Enable AWD.
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} en_adc_awden_t;
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/**
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*******************************************************************************
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** \brief PGA control.
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**
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******************************************************************************/
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typedef enum en_adc_pga_ctl
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{
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AdcPgaCtl_Invalid = 0x0, ///< Amplifier is invalid.
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AdcPgaCtl_Amplify = 0xE, ///< Amplifier effective.
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} en_adc_pga_ctl_t;
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/**
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*******************************************************************************
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** \brief The amplification factor of the amplifier is as follows.
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**
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******************************************************************************/
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typedef enum en_adc_pga_factor
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{
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AdcPgaFactor_2 = 0x0, ///< PGA magnification 2.
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AdcPgaFactor_2P133 = 0x1, ///< PGA magnification 2.133.
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AdcPgaFactor_2P286 = 0x2, ///< PGA magnification 2.286.
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AdcPgaFactor_2P667 = 0x3, ///< PGA magnification 2.667.
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AdcPgaFactor_2P909 = 0x4, ///< PGA magnification 2.909.
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AdcPgaFactor_3P2 = 0x5, ///< PGA magnification 3.2.
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AdcPgaFactor_3P556 = 0x6, ///< PGA magnification 3.556.
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AdcPgaFactor_4 = 0x7, ///< PGA magnification 4.
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AdcPgaFactor_4P571 = 0x8, ///< PGA magnification 4.571.
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AdcPgaFactor_5P333 = 0x9, ///< PGA magnification 5.333.
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AdcPgaFactor_6P4 = 0xA, ///< PGA magnification 6.4.
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AdcPgaFactor_8 = 0xB, ///< PGA magnification 8.
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AdcPgaFactor_10P667 = 0xC, ///< PGA magnification 10.667.
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AdcPgaFactor_16 = 0xD, ///< PGA magnification 16.
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AdcPgaFactor_32 = 0xE, ///< PGA magnification 32.
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} en_adc_pga_factor_t;
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/**
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*******************************************************************************
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** \brief Negative phase input selection
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**
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******************************************************************************/
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typedef enum en_adc_pga_negative
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{
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AdcPgaNegative_PGAVSS = 0x0, ///< Use external port PGAVSS as PGA negative input.
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AdcPgaNegative_VSSA = 0x1, ///< Use internal analog ground VSSA as PGA negative input.
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} en_adc_pga_negative_t;
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/**
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*******************************************************************************
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** \brief ADC common trigger source select
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**
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******************************************************************************/
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typedef enum en_adc_com_trigger
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{
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AdcComTrigger_1 = 0x1, ///< Select common trigger 1.
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AdcComTrigger_2 = 0x2, ///< Select common trigger 2.
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AdcComTrigger_1_2 = 0x3, ///< Select common trigger 1 and 2.
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} en_adc_com_trigger_t;
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/**
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*******************************************************************************
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** \brief Structure definition of ADC
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**
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******************************************************************************/
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typedef struct stc_adc_ch_cfg
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{
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uint32_t u32Channel; ///< ADC channels mask.
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uint8_t u8Sequence; ///< The sequence which the channel(s) belong to.
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uint8_t *pu8SampTime; ///< Pointer to sampling time.
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} stc_adc_ch_cfg_t;
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typedef struct stc_adc_awd_cfg
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{
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en_adc_awdmd_t enAwdmd; ///< Comparison mode of the values.
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en_adc_awdss_t enAwdss; ///< Interrupt output select.
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uint16_t u16AwdDr0; ///< Your range DR0.
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uint16_t u16AwdDr1; ///< Your range DR1.
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} stc_adc_awd_cfg_t;
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typedef struct stc_adc_trg_cfg
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{
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uint8_t u8Sequence; ///< The sequence will be configured trigger source.
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en_adc_trgsel_t enTrgSel; ///< Trigger source type.
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en_event_src_t enInTrg0; ///< Internal trigger 0 source number
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///< (event number @ref en_event_src_t).
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en_event_src_t enInTrg1; ///< Internal trigger 1 source number
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///< (event number @ref en_event_src_t).
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} stc_adc_trg_cfg_t;
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typedef struct stc_adc_init
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{
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en_adc_resolution_t enResolution; ///< ADC resolution 12bit/10bit/8bit.
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en_adc_data_align_t enDataAlign; ///< ADC data alignment.
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en_adc_clren_t enAutoClear; ///< Automatically clear data register.
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///< after reading data register(enable/disable).
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en_adc_scan_mode_t enScanMode; ///< ADC scan mode.
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en_adc_rschsel_t enRschsel; ///< Restart or continue.
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} stc_adc_init_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief ADC sequence definition.
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**
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******************************************************************************/
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/* ADC sequence definition */
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#define ADC_SEQ_A ((uint8_t)0)
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#define ADC_SEQ_B ((uint8_t)1)
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/* ADC pin definition */
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#define ADC1_IN0 ((uint8_t)0)
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#define ADC1_IN1 ((uint8_t)1)
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#define ADC1_IN2 ((uint8_t)2)
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#define ADC1_IN3 ((uint8_t)3)
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#define ADC12_IN4 ((uint8_t)4)
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#define ADC12_IN5 ((uint8_t)5)
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#define ADC12_IN6 ((uint8_t)6)
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#define ADC12_IN7 ((uint8_t)7)
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#define ADC12_IN8 ((uint8_t)8)
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#define ADC12_IN9 ((uint8_t)9)
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#define ADC12_IN10 ((uint8_t)10)
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#define ADC12_IN11 ((uint8_t)11)
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#define ADC1_IN12 ((uint8_t)12)
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#define ADC1_IN13 ((uint8_t)13)
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#define ADC1_IN14 ((uint8_t)14)
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#define ADC1_IN15 ((uint8_t)15)
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#define ADC_PIN_INVALID ((uint8_t)0xFF)
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/* ADC channel index definition */
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#define ADC_CH_IDX0 (0u)
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#define ADC_CH_IDX1 (1u)
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#define ADC_CH_IDX2 (2u)
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#define ADC_CH_IDX3 (3u)
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#define ADC_CH_IDX4 (4u)
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#define ADC_CH_IDX5 (5u)
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#define ADC_CH_IDX6 (6u)
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#define ADC_CH_IDX7 (7u)
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#define ADC_CH_IDX8 (8u)
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#define ADC_CH_IDX9 (9u)
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#define ADC_CH_IDX10 (10u)
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#define ADC_CH_IDX11 (11u)
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#define ADC_CH_IDX12 (12u)
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#define ADC_CH_IDX13 (13u)
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#define ADC_CH_IDX14 (14u)
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#define ADC_CH_IDX15 (15u)
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#define ADC_CH_IDX16 (16u)
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/* ADC1 channel mask definition */
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#define ADC1_CH0 (0x1ul << 0u) ///< Default mapping pin ADC1_IN0
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#define ADC1_CH1 (0x1ul << 1u) ///< Default mapping pin ADC1_IN1
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#define ADC1_CH2 (0x1ul << 2u) ///< Default mapping pin ADC1_IN2
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#define ADC1_CH3 (0x1ul << 3u) ///< Default mapping pin ADC1_IN3
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#define ADC1_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN4
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#define ADC1_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN5
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#define ADC1_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN6
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#define ADC1_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN7
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#define ADC1_CH8 (0x1ul << 8u) ///< Default mapping pin ADC12_IN8
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#define ADC1_CH9 (0x1ul << 9u) ///< Default mapping pin ADC12_IN9
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#define ADC1_CH10 (0x1ul << 10u) ///< Default mapping pin ADC12_IN10
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#define ADC1_CH11 (0x1ul << 11u) ///< Default mapping pin ADC12_IN11
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#define ADC1_CH12 (0x1ul << 12u) ///< Default mapping pin ADC12_IN12
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#define ADC1_CH13 (0x1ul << 13u) ///< Default mapping pin ADC12_IN13
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#define ADC1_CH14 (0x1ul << 14u) ///< Default mapping pin ADC12_IN14
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#define ADC1_CH15 (0x1ul << 15u) ///< Default mapping pin ADC12_IN15
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#define ADC1_CH16 (0x1ul << 16u)
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#define ADC1_CH_INTERNAL (ADC1_CH16) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC
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#define ADC1_CH_ALL (0x0001FFFFul)
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#define ADC1_PIN_MASK_ALL (ADC1_CH_ALL & ~ADC1_CH_INTERNAL)
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/* ADC2 channel definition */
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#define ADC2_CH0 (0x1ul << 0u) ///< Default mapping pin ADC12_IN4
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#define ADC2_CH1 (0x1ul << 1u) ///< Default mapping pin ADC12_IN5
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#define ADC2_CH2 (0x1ul << 2u) ///< Default mapping pin ADC12_IN6
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#define ADC2_CH3 (0x1ul << 3u) ///< Default mapping pin ADC12_IN7
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#define ADC2_CH4 (0x1ul << 4u) ///< Default mapping pin ADC12_IN8
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#define ADC2_CH5 (0x1ul << 5u) ///< Default mapping pin ADC12_IN9
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#define ADC2_CH6 (0x1ul << 6u) ///< Default mapping pin ADC12_IN10
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#define ADC2_CH7 (0x1ul << 7u) ///< Default mapping pin ADC12_IN11
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#define ADC2_CH8 (0x1ul << 8u)
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#define ADC2_CH_INTERNAL (ADC2_CH8) ///< 8bit DAC_1/DAC_2 or internal VERF, dependent on CMP_RVADC
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#define ADC2_CH_ALL (0x000001FFul)
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#define ADC2_PIN_MASK_ALL (ADC2_CH_ALL & ~ADC2_CH_INTERNAL)
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/*
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* PGA channel definition.
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* NOTE: The PGA channel directly maps external pins and does not correspond to the ADC channel.
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*/
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#define PGA_CH0 (0x1ul << ADC1_IN0) ///< Mapping pin ADC1_IN0
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#define PGA_CH1 (0x1ul << ADC1_IN1) ///< Mapping pin ADC1_IN1
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#define PGA_CH2 (0x1ul << ADC1_IN2) ///< Mapping pin ADC1_IN2
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#define PGA_CH3 (0x1ul << ADC1_IN3) ///< Mapping pin ADC1_IN3
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#define PGA_CH4 (0x1ul << ADC12_IN4) ///< Mapping pin ADC12_IN4
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#define PGA_CH5 (0x1ul << ADC12_IN5) ///< Mapping pin ADC12_IN5
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#define PGA_CH6 (0x1ul << ADC12_IN6) ///< Mapping pin ADC12_IN6
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#define PGA_CH7 (0x1ul << ADC12_IN7) ///< Mapping pin ADC12_IN7
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#define PGA_CH8 (0x1ul << ADC12_IN8) ///< Mapping internal 8bit DAC1 output
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#define PGA_CH_ALL (0x000001FFul)
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/* ADC1 has up to 17 channels */
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#define ADC1_CH_COUNT (17u)
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/* ADC2 has up to 9 channels */
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#define ADC2_CH_COUNT (9u)
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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* Global function prototypes (definition in C source)
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******************************************************************************/
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en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit);
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en_result_t ADC_DeInit(M4_ADC_TypeDef *ADCx);
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en_result_t ADC_SetScanMode(M4_ADC_TypeDef *ADCx, en_adc_scan_mode_t enMode);
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en_result_t ADC_ConfigTriggerSrc(M4_ADC_TypeDef *ADCx, const stc_adc_trg_cfg_t *pstcTrgCfg);
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en_result_t ADC_TriggerSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState);
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void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, en_adc_trgsel_t enTrgSel, \
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en_adc_com_trigger_t enComTrigger, en_functional_state_t enState);
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en_result_t ADC_AddAdcChannel(M4_ADC_TypeDef *ADCx, const stc_adc_ch_cfg_t *pstcChCfg);
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en_result_t ADC_DelAdcChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
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en_result_t ADC_SeqITCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enState);
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en_result_t ADC_ConfigAvg(M4_ADC_TypeDef *ADCx, en_adc_avcnt_t enAvgCnt);
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en_result_t ADC_AddAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
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en_result_t ADC_DelAvgChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
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en_result_t ADC_ConfigAwd(M4_ADC_TypeDef *ADCx, const stc_adc_awd_cfg_t *pstcAwdCfg);
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en_result_t ADC_AwdCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState);
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en_result_t ADC_AwdITCmd(M4_ADC_TypeDef *ADCx, en_functional_state_t enState);
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en_result_t ADC_AddAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
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en_result_t ADC_DelAwdChannel(M4_ADC_TypeDef *ADCx, uint32_t u32Channel);
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void ADC_ConfigPga(en_adc_pga_factor_t enFactor, en_adc_pga_negative_t enNegativeIn);
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void ADC_PgaCmd(en_functional_state_t enState);
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void ADC_AddPgaChannel(uint32_t u32Channel);
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void ADC_DelPgaChannel(uint32_t u32Channel);
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void ADC_ConfigSync(en_adc_sync_mode_t enMode, uint8_t u8TrgDelay);
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void ADC_SyncCmd(en_functional_state_t enState);
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en_result_t ADC_StartConvert(M4_ADC_TypeDef *ADCx);
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en_result_t ADC_StopConvert(M4_ADC_TypeDef *ADCx);
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en_flag_status_t ADC_GetEocFlag(const M4_ADC_TypeDef *ADCx, uint8_t u8Seq);
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void ADC_ClrEocFlag(M4_ADC_TypeDef *ADCx, uint8_t u8Seq);
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en_result_t ADC_PollingSa(M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length, uint32_t u32Timeout);
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en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t *pu16AdcData, uint8_t u8Length);
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en_result_t ADC_GetChData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, uint16_t *pu16AdcData, uint8_t u8Length);
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uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex);
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uint32_t ADC_GetAwdFlag(const M4_ADC_TypeDef *ADCx);
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void ADC_ClrAwdFlag(M4_ADC_TypeDef *ADCx);
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void ADC_ClrAwdChFlag(M4_ADC_TypeDef *ADCx, uint32_t u32AwdCh);
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en_result_t ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32DestChannel, uint8_t u8AdcPin);
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uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint8_t u8ChIndex);
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//@} // AdcGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* DDL_ADC_ENABLE */
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#endif /* __HC32F460_ADC_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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