160 lines
3.4 KiB
C
160 lines
3.4 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-09-06 勤为本 first version
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*/
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#include "ls1c_regs.h"
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#include "ls1c_public.h"
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// 晶振的频率
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#define AHB_CLK (24000000)
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#define APB_CLK (AHB_CLK)
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// START_FREQ寄存器bits
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#define M_PLL_SHIFT (8)
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#define M_PLL (0xff << M_PLL_SHIFT) // PLL倍频系数的整数部分
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#define FRAC_N_SHIFT (16)
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#define FRAC_N (0xff << FRAC_N_SHIFT) // PLL倍频系数的小数部分
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#define DIV_SDRAM_SHIFT (0)
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#define DIV_SDRAM (0x3 << DIV_SDRAM_SHIFT)
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// CLK_DIV_PARAM寄存器bits
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#define DIV_PIX_EN (0x1 << 31)
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#define DIV_PIX (0x7f << 24)
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#define DIV_CAM_EN (0x1 << 23)
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#define DIV_CAM (0x7f << 16)
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#define DIV_CPU_EN (0x1 << 15)
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#define DIV_CPU (0x7f << 8)
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#define DIV_PIX_VALID (0x1 << 5)
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#define DIV_PIX_SEL (0x1 << 4)
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#define DIV_CAM_VALID (0x1 << 3)
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#define DIV_CAM_SEL (0x1 << 2)
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#define DIV_CPU_VALID (0x1 << 1)
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#define DIV_CPU_SEL (0x1 << 0)
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#define DIV_PIX_SHIFT (24)
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#define DIV_CAM_SHIFT (16)
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#define DIV_CPU_SHIFT (8)
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/*
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* 获取PLL频率
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* @ret PLL频率
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*/
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unsigned long clk_get_pll_rate(void)
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{
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unsigned int ctrl;
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unsigned long pll_rate = 0;
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ctrl = reg_read_32((volatile unsigned int *)LS1C_START_FREQ);
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pll_rate = (((ctrl & M_PLL) >> M_PLL_SHIFT) + ((ctrl & FRAC_N) >> FRAC_N_SHIFT)) * APB_CLK / 4;
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return pll_rate;
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}
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/*
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* 获取CPU频率
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* @ret CPU频率
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*/
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unsigned long clk_get_cpu_rate(void)
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{
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unsigned long pll_rate, cpu_rate;
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unsigned int ctrl;
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pll_rate = clk_get_pll_rate();
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ctrl = reg_read_32((volatile unsigned int *)LS1C_CLK_DIV_PARAM);
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// 选择时钟来源
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if (DIV_CPU_SEL & ctrl) // pll分频作为时钟信号
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{
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if (DIV_CPU_EN & ctrl)
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{
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cpu_rate = pll_rate / ((ctrl & DIV_CPU) >> DIV_CPU_SHIFT);
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}
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else
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{
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cpu_rate = pll_rate / 2;
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}
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}
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else // bypass模式，晶振作为时钟输入
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{
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cpu_rate = APB_CLK;
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}
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return cpu_rate;
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}
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/*
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* 获取DDR频率
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* @ret DDR频率
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*/
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unsigned long clk_get_ddr_rate(void)
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{
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unsigned long cpu_rate = 0;
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unsigned long ddr_rate = 0;
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unsigned int ctrl;
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cpu_rate = clk_get_cpu_rate();
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ctrl = reg_read_32((volatile unsigned int *)LS1C_START_FREQ);
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ctrl = (ctrl & DIV_SDRAM) >> DIV_SDRAM_SHIFT;
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switch (ctrl)
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{
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case 0:
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ddr_rate = cpu_rate / 2;
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break;
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case 1:
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ddr_rate = cpu_rate / 4;
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break;
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case 2:
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case 3:
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ddr_rate = cpu_rate / 3;
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break;
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}
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return ddr_rate;
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}
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/*
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* 获取APB频率
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* @ret APB频率
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*/
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unsigned long clk_get_apb_rate(void)
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{
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return clk_get_ddr_rate();
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}
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/*
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* 获取DC频率
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* @ret DC频率
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*/
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unsigned long clk_get_dc_rate(void)
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{
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unsigned long pll_rate, dc_rate;
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unsigned int ctrl;
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pll_rate = clk_get_pll_rate();
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ctrl = reg_read_32((volatile unsigned int *)LS1C_CLK_DIV_PARAM);
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dc_rate = pll_rate / ((ctrl & DIV_PIX) >> DIV_PIX_SHIFT);
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return dc_rate;
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}
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