334 lines
7.4 KiB
C
334 lines
7.4 KiB
C
/*
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* File : drv_uart.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009-2014 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2013-05-18 Bernard The first version for LPC40xx
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* 2014-12-16 RT_learning The first version for LPC5410x
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "chip.h"
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static uint32_t _UART_DivClk(uint32_t pclk, uint32_t m);
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static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict);
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static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev);
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static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub);
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static void _UART_CalcMul(UART_BAUD_T *ub);
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struct lpc_uart
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{
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LPC_USART_T *UART;
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IRQn_Type UART_IRQn;
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};
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static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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struct lpc_uart *uart;
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UART_BAUD_T baud;
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UART_CFG_T UART_cfg;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct lpc_uart *)serial->parent.user_data;
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/* Initialize UART Configuration parameter structure to default state:
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* Baudrate = 115200 b
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* 8 data bit
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* 1 Stop bit
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* None parity
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*/
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/* Set up baudrate parameters */
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baud.clk = Chip_Clock_GetAsyncSyscon_ClockRate(); /* Clock frequency */
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baud.baud = cfg->baud_rate; /* Required baud rate */
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baud.ovr = 0; /* Set the oversampling to the recommended rate */
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baud.mul = baud.div = 0;
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if(!baud.mul)
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{
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_UART_CalcMul(&baud);
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}
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_UART_CalcDiv(&baud);
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/* Set fractional control register */
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LPC_ASYNC_SYSCON->FRGCTRL = ((uint32_t) baud.mul << 8) | 0xFF;
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/* Configure the UART */
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UART_cfg.cfg = UART_CFG_8BIT;
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UART_cfg.div = baud.div; /* Use the calculated div value */
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UART_cfg.ovr = baud.ovr; /* Use oversampling rate from baud */
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UART_cfg.res = UART_BIT_DLY(cfg->baud_rate);
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/* P254,255,246 */
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uart->UART->OSR = (UART_cfg.ovr - 1) & 0x0F;
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uart->UART->BRG = (UART_cfg.div - 1) & 0xFFFF;
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uart->UART->CFG = UART_CFG_ENABLE | (UART_cfg.cfg & ~UART_CFG_RES);
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return RT_EOK;
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}
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static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct lpc_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct lpc_uart *)serial->parent.user_data;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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uart->UART->INTENCLR &= ~0x01;
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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uart->UART->INTENSET |= 0x01;
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break;
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}
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return RT_EOK;
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}
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static int lpc_putc(struct rt_serial_device *serial, char c)
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{
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struct lpc_uart *uart;
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uart = (struct lpc_uart *)serial->parent.user_data;
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while(!(uart->UART->STAT & (0x01<<2)));
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uart->UART->TXDAT = c ;
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return 1;
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}
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static int lpc_getc(struct rt_serial_device *serial)
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{
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struct lpc_uart *uart;
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uart = (struct lpc_uart *)serial->parent.user_data;
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if (uart->UART->STAT & 0x01)
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return (uart->UART->RXDAT);
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else
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return -1;
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}
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static const struct rt_uart_ops lpc_uart_ops =
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{
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lpc_configure,
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lpc_control,
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lpc_putc,
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lpc_getc,
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};
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/* UART0 device driver structure */
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struct lpc_uart uart0 =
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{
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LPC_USART0,
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UART0_IRQn,
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};
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struct rt_serial_device serial0;
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void UART0_IRQHandler(void)
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{
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volatile uint32_t INTSTAT, tmp;
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/* enter interrupt */
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rt_interrupt_enter();
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INTSTAT = LPC_USART0->INTSTAT;
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INTSTAT &= 0x01;
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switch (INTSTAT)
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{
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case 0x01:
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rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
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break;
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default :
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tmp = LPC_USART0->INTSTAT;
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break;
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void rt_hw_uart_init(void)
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{
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struct lpc_uart *uart;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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uart = &uart0;
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serial0.ops = &lpc_uart_ops;
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serial0.config = config;
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serial0.parent.user_data = uart;
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/* Enable IOCON clock Then your cfg will effective P38 */
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LPC_SYSCON->AHBCLKCTRLSET[0] = (1UL << 13);
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/* Setup UART TX,RX Pin configuration cfg Pin as Tx, Rx */
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/* P63,P77
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Selects pin function 1 IOCON_FUNC1
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No addition pin function IOCON_MODE_INACT
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Enables digital function by setting 1 to bit 7(default) IOCON_DIGITAL_EN
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*/
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LPC_IOCON->PIO[0][0] = (0x1 | (0x0 << 3) | (0x1 << 7));
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LPC_IOCON->PIO[0][1] = (0x1 | (0x0 << 3) | (0x1 << 7));
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/* Enable asynchronous APB bridge and subsystem P30 */
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LPC_SYSCON->ASYNCAPBCTRL = 0x01;
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/* The UART clock rate is the main system clock divided by this value P59 */
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LPC_ASYNC_SYSCON->ASYNCCLKDIV = 1; /* Set Async clock divider to 1 */
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/* Enable peripheral clock(asynchronous APB) to UART0 P57*/
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LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << 0x01);
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/* Controls the clock for the Fractional Rate Generator used with the USARTs P57*/
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LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << 0x0F); /* Enable clock to Fractional divider */
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/* preemption = 1, sub-priority = 1 */
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NVIC_SetPriority(uart->UART_IRQn, ((0x01 << 3) | 0x01));
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/* Enable Interrupt for UART channel */
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NVIC_EnableIRQ(uart->UART_IRQn);
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/* register UART0 device */
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rt_hw_serial_register(&serial0, "uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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uart);
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}
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/* PRIVATE: Division logic to divide without integer overflow */
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static uint32_t _UART_DivClk(uint32_t pclk, uint32_t m)
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{
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uint32_t q, r, u = pclk >> 24, l = pclk << 8;
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m = m + 256;
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q = (1 << 24) / m;
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r = (1 << 24) - (q * m);
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return ((q * u) << 8) + (((r * u) << 8) + l) / m;
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}
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/* PRIVATE: Get highest Over sampling value */
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static uint32_t _UART_GetHighDiv(uint32_t val, uint8_t strict)
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{
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int32_t i, max = strict ? 16 : 5;
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for (i = 16; i >= max; i--) {
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if (!(val % i)) {
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return i;
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}
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}
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return 0;
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}
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/* Calculate error difference */
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static int32_t _CalcErr(uint32_t n, uint32_t d, uint32_t *prev)
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{
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uint32_t err = n - (n / d) * d;
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uint32_t herr = ((n / d) + 1) * d - n;
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if (herr < err) {
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err = herr;
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}
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if (*prev <= err) {
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return 0;
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}
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*prev = err;
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return (herr == err) + 1;
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}
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/* Calculate the base DIV value */
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static ErrorCode_t _UART_CalcDiv(UART_BAUD_T *ub)
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{
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int32_t i = 0;
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uint32_t perr = ~0UL;
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if (!ub->div) {
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i = ub->ovr ? ub->ovr : 16;
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}
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for (; i > 4; i--) {
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int32_t tmp = _CalcErr(ub->clk, ub->baud * i, &perr);
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/* Continue when no improvement seen in err value */
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if (!tmp) {
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continue;
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}
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ub->div = tmp - 1;
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if (ub->ovr == i) {
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break;
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}
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ub->ovr = i;
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}
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if (!ub->ovr) {
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return ERR_UART_BAUDRATE;
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}
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ub->div += ub->clk / (ub->baud * ub->ovr);
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if (!ub->div) {
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return ERR_UART_BAUDRATE;
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}
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ub->baud = ub->clk / (ub->div * ub->ovr);
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return LPC_OK;
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}
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/* Calculate the best MUL value */
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static void _UART_CalcMul(UART_BAUD_T *ub)
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{
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uint32_t m, perr = ~0UL, pclk = ub->clk, ovr = ub->ovr;
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/* If clock is UART's base clock calculate only the divider */
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for (m = 0; m < 256; m++) {
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uint32_t ov = ovr, x, v, tmp;
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/* Get clock and calculate error */
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x = _UART_DivClk(pclk, m);
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tmp = _CalcErr(x, ub->baud, &perr);
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v = (x / ub->baud) + tmp - 1;
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/* Update if new error is better than previous best */
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if (!tmp || (ovr && (v % ovr)) ||
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(!ovr && ((ov = _UART_GetHighDiv(v, ovr)) == 0))) {
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continue;
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}
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ub->ovr = ov;
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ub->mul = m;
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ub->clk = x;
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ub->div = tmp - 1;
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}
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}
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