80 lines
1.4 KiB
C
80 lines
1.4 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-26 huanghe first commit
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*
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*/
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#ifndef __PHYTIUM_CPU_H__
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#define __PHYTIUM_CPU_H__
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#include <rthw.h>
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#include <rtthread.h>
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#include "fparameters.h"
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#define ARM_GIC_MAX_NR 1
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#define MAX_HANDLERS 160
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#define GIC_IRQ_START 0
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#define GIC_ACK_INTID_MASK 0x000003ff
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rt_uint64_t get_main_cpu_affval(void);
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rt_inline rt_uint32_t platform_get_gic_dist_base(void)
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{
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return GICV3_DISTRIBUTOR_BASEADDRESS;
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}
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#if defined(TARGET_ARMV8_AARCH64)
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/* the basic constants and interfaces needed by gic */
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rt_inline rt_uint32_t platform_get_gic_redist_base(void)
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{
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extern int phytium_cpu_id(void);
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s32 cpu_offset = 0;
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#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
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cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
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#endif
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#if defined(TARGET_E2000Q)
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u32 cpu_id = 0;
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cpu_id = phytium_cpu_id();
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switch (cpu_id)
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{
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case 0:
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case 1:
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cpu_offset = 2;
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break;
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case 2:
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case 3:
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cpu_offset = -2;
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default:
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break;
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}
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#endif
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rt_kprintf("offset is %x\n", cpu_offset);
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return (GICV3_RD_BASEADDRESS + (cpu_offset) * GICV3_RD_OFFSET);
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}
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rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
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{
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return 0U; /* unused in gicv3 */
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}
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#endif
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int phytium_cpu_id_mapping(int cpu_id);
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#endif // !
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