815 lines
27 KiB
C
815 lines
27 KiB
C
/*
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* Copyright (c) 2021-2024 HPMicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef HPM_SOC_H
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#define HPM_SOC_H
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/* List of external IRQs */
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#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */
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#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */
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#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */
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#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */
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#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */
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#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */
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#define IRQn_GPIO0_X 7 /* GPIO0_X IRQ */
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#define IRQn_GPIO0_Y 8 /* GPIO0_Y IRQ */
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#define IRQn_GPIO0_Z 9 /* GPIO0_Z IRQ */
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#define IRQn_MCAN0 10 /* MCAN0 IRQ */
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#define IRQn_MCAN1 11 /* MCAN1 IRQ */
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#define IRQn_MCAN2 12 /* MCAN2 IRQ */
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#define IRQn_MCAN3 13 /* MCAN3 IRQ */
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#define IRQn_MCAN4 14 /* MCAN4 IRQ */
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#define IRQn_MCAN5 15 /* MCAN5 IRQ */
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#define IRQn_MCAN6 16 /* MCAN6 IRQ */
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#define IRQn_MCAN7 17 /* MCAN7 IRQ */
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#define IRQn_PTPC 18 /* PTPC IRQ */
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#define IRQn_UART0 27 /* UART0 IRQ */
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#define IRQn_UART1 28 /* UART1 IRQ */
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#define IRQn_UART2 29 /* UART2 IRQ */
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#define IRQn_UART3 30 /* UART3 IRQ */
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#define IRQn_UART4 31 /* UART4 IRQ */
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#define IRQn_UART5 32 /* UART5 IRQ */
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#define IRQn_UART6 33 /* UART6 IRQ */
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#define IRQn_UART7 34 /* UART7 IRQ */
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#define IRQn_I2C0 35 /* I2C0 IRQ */
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#define IRQn_I2C1 36 /* I2C1 IRQ */
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#define IRQn_I2C2 37 /* I2C2 IRQ */
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#define IRQn_I2C3 38 /* I2C3 IRQ */
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#define IRQn_SPI0 39 /* SPI0 IRQ */
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#define IRQn_SPI1 40 /* SPI1 IRQ */
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#define IRQn_SPI2 41 /* SPI2 IRQ */
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#define IRQn_SPI3 42 /* SPI3 IRQ */
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#define IRQn_GPTMR0 43 /* GPTMR0 IRQ */
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#define IRQn_GPTMR1 44 /* GPTMR1 IRQ */
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#define IRQn_GPTMR2 45 /* GPTMR2 IRQ */
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#define IRQn_GPTMR3 46 /* GPTMR3 IRQ */
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#define IRQn_GPTMR4 47 /* GPTMR4 IRQ */
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#define IRQn_GPTMR5 48 /* GPTMR5 IRQ */
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#define IRQn_GPTMR6 49 /* GPTMR6 IRQ */
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#define IRQn_GPTMR7 50 /* GPTMR7 IRQ */
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#define IRQn_EWDG0 51 /* EWDG0 IRQ */
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#define IRQn_EWDG1 52 /* EWDG1 IRQ */
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#define IRQn_MBX0A 53 /* MBX0A IRQ */
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#define IRQn_MBX0B 54 /* MBX0B IRQ */
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#define IRQn_MBX1A 55 /* MBX1A IRQ */
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#define IRQn_MBX1B 56 /* MBX1B IRQ */
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#define IRQn_RNG 57 /* RNG IRQ */
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#define IRQn_HDMA 58 /* HDMA IRQ */
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#define IRQn_ADC0 59 /* ADC0 IRQ */
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#define IRQn_ADC1 60 /* ADC1 IRQ */
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#define IRQn_SDM 61 /* SDM IRQ */
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#define IRQn_OPAMP 62 /* OPAMP IRQ */
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#define IRQn_I2S0 63 /* I2S0 IRQ */
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#define IRQn_I2S1 64 /* I2S1 IRQ */
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#define IRQn_I2S2 65 /* I2S2 IRQ */
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#define IRQn_I2S3 66 /* I2S3 IRQ */
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#define IRQn_DAO 67 /* DAO IRQ */
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#define IRQn_PDM 68 /* PDM IRQ */
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#define IRQn_SMIX_DMA 69 /* SMIX_DMA IRQ */
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#define IRQn_SMIX_ASRC 70 /* SMIX_ASRC IRQ */
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#define IRQn_CAM0 71 /* CAM0 IRQ */
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#define IRQn_CAM1 72 /* CAM1 IRQ */
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#define IRQn_LCDC 73 /* LCDC IRQ */
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#define IRQn_LCDC1 74 /* LCDC1 IRQ */
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#define IRQn_PDMA 75 /* PDMA IRQ */
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#define IRQn_JPEG 76 /* JPEG IRQ */
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#define IRQn_GWCK0_FUNC 77 /* GWCK0_FUNC IRQ */
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#define IRQn_GWCK0_ERR 78 /* GWCK0_ERR IRQ */
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#define IRQn_GWCK1_FUNC 79 /* GWCK1_FUNC IRQ */
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#define IRQn_GWCK1_ERR 80 /* GWCK1_ERR IRQ */
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#define IRQn_MIPI_DSI0 81 /* MIPI_DSI0 IRQ */
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#define IRQn_MIPI_DSI1 82 /* MIPI_DSI1 IRQ */
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#define IRQn_MIPI_CSI0 83 /* MIPI_CSI0 IRQ */
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#define IRQn_MIPI_CSI0_AP 84 /* MIPI_CSI0_AP IRQ */
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#define IRQn_MIPI_CSI0_DIAG 85 /* MIPI_CSI0_DIAG IRQ */
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#define IRQn_MIPI_CSI1_AP 86 /* MIPI_CSI1_AP IRQ */
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#define IRQn_MIPI_CSI1_DIAG 87 /* MIPI_CSI1_DIAG IRQ */
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#define IRQn_MIPI_CSI1 88 /* MIPI_CSI1 IRQ */
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#define IRQn_LCB0 89 /* LCB0 IRQ */
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#define IRQn_LCB1 90 /* LCB1 IRQ */
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#define IRQn_GPU 91 /* GPU IRQ */
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#define IRQn_ENET0 92 /* ENET0 IRQ */
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#define IRQn_NTMR0 93 /* NTMR0 IRQ */
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#define IRQn_USB0 94 /* USB0 IRQ */
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#define IRQn_SDXC0 95 /* SDXC0 IRQ */
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#define IRQn_SDXC1 96 /* SDXC1 IRQ */
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#define IRQn_SDP 97 /* SDP IRQ */
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#define IRQn_XPI0 98 /* XPI0 IRQ */
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#define IRQn_XDMA 99 /* XDMA IRQ */
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#define IRQn_DDR 100 /* DDR IRQ */
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#define IRQn_FFA 101 /* FFA IRQ */
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#define IRQn_PSEC 102 /* PSEC IRQ */
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#define IRQn_TSNS 103 /* TSNS IRQ */
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#define IRQn_VAD 104 /* VAD IRQ */
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#define IRQn_PGPIO 105 /* PGPIO IRQ */
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#define IRQn_PWDG 106 /* PWDG IRQ */
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#define IRQn_PTMR 107 /* PTMR IRQ */
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#define IRQn_PUART 108 /* PUART IRQ */
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#define IRQn_FUSE 109 /* FUSE IRQ */
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#define IRQn_SECMON 110 /* SECMON IRQ */
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#define IRQn_RTC 111 /* RTC IRQ */
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#define IRQn_BGPIO 112 /* BGPIO IRQ */
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#define IRQn_BVIO 113 /* BVIO IRQ */
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#define IRQn_BROWNOUT 114 /* BROWNOUT IRQ */
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#define IRQn_SYSCTL 115 /* SYSCTL IRQ */
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#define IRQn_DEBUG0 116 /* DEBUG0 IRQ */
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#define IRQn_DEBUG1 117 /* DEBUG1 IRQ */
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#include "hpm_common.h"
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#include "hpm_gpio_regs.h"
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/* Address of GPIO instances */
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/* FGPIO base address */
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#define HPM_FGPIO_BASE (0xC0000UL)
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/* FGPIO base pointer */
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#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE)
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/* GPIO0 base address */
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#define HPM_GPIO0_BASE (0xF00D0000UL)
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/* GPIO0 base pointer */
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#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE)
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/* PGPIO base address */
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#define HPM_PGPIO_BASE (0xF411C000UL)
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/* PGPIO base pointer */
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#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE)
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/* BGPIO base address */
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#define HPM_BGPIO_BASE (0xF4214000UL)
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/* BGPIO base pointer */
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#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE)
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/* Address of DM instances */
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/* DM base address */
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#define HPM_DM_BASE (0x30000000UL)
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#include "hpm_plic_regs.h"
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/* Address of PLIC instances */
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/* PLIC base address */
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#define HPM_PLIC_BASE (0xE4000000UL)
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/* PLIC base pointer */
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#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE)
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#include "hpm_mchtmr_regs.h"
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/* Address of MCHTMR instances */
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/* MCHTMR base address */
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#define HPM_MCHTMR_BASE (0xE6000000UL)
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/* MCHTMR base pointer */
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#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE)
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#include "hpm_plic_sw_regs.h"
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/* Address of PLICSW instances */
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/* PLICSW base address */
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#define HPM_PLICSW_BASE (0xE6400000UL)
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/* PLICSW base pointer */
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#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE)
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#include "hpm_crc_regs.h"
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/* Address of CRC instances */
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/* CRC base address */
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#define HPM_CRC_BASE (0xF000C000UL)
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/* CRC base pointer */
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#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE)
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#include "hpm_uart_regs.h"
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/* Address of UART instances */
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/* UART0 base address */
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#define HPM_UART0_BASE (0xF0040000UL)
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/* UART0 base pointer */
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#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE)
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/* UART1 base address */
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#define HPM_UART1_BASE (0xF0044000UL)
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/* UART1 base pointer */
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#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE)
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/* UART2 base address */
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#define HPM_UART2_BASE (0xF0048000UL)
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/* UART2 base pointer */
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#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE)
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/* UART3 base address */
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#define HPM_UART3_BASE (0xF004C000UL)
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/* UART3 base pointer */
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#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE)
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/* UART4 base address */
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#define HPM_UART4_BASE (0xF0050000UL)
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/* UART4 base pointer */
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#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE)
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/* UART5 base address */
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#define HPM_UART5_BASE (0xF0054000UL)
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/* UART5 base pointer */
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#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE)
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/* UART6 base address */
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#define HPM_UART6_BASE (0xF0058000UL)
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/* UART6 base pointer */
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#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE)
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/* UART7 base address */
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#define HPM_UART7_BASE (0xF005C000UL)
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/* UART7 base pointer */
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#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE)
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/* PUART base address */
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#define HPM_PUART_BASE (0xF4124000UL)
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/* PUART base pointer */
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#define HPM_PUART ((UART_Type *) HPM_PUART_BASE)
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#include "hpm_i2c_regs.h"
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/* Address of I2C instances */
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/* I2C0 base address */
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#define HPM_I2C0_BASE (0xF0060000UL)
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/* I2C0 base pointer */
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#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE)
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/* I2C1 base address */
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#define HPM_I2C1_BASE (0xF0064000UL)
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/* I2C1 base pointer */
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#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE)
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/* I2C2 base address */
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#define HPM_I2C2_BASE (0xF0068000UL)
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/* I2C2 base pointer */
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#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE)
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/* I2C3 base address */
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#define HPM_I2C3_BASE (0xF006C000UL)
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/* I2C3 base pointer */
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#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE)
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#include "hpm_spi_regs.h"
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/* Address of SPI instances */
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/* SPI0 base address */
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#define HPM_SPI0_BASE (0xF0070000UL)
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/* SPI0 base pointer */
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#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE)
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/* SPI1 base address */
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#define HPM_SPI1_BASE (0xF0074000UL)
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/* SPI1 base pointer */
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#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE)
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/* SPI2 base address */
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#define HPM_SPI2_BASE (0xF0078000UL)
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/* SPI2 base pointer */
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#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE)
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/* SPI3 base address */
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#define HPM_SPI3_BASE (0xF007C000UL)
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/* SPI3 base pointer */
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#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE)
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#include "hpm_gptmr_regs.h"
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/* Address of TMR instances */
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/* GPTMR0 base address */
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#define HPM_GPTMR0_BASE (0xF0080000UL)
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/* GPTMR0 base pointer */
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#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE)
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/* GPTMR1 base address */
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#define HPM_GPTMR1_BASE (0xF0084000UL)
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/* GPTMR1 base pointer */
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#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE)
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/* GPTMR2 base address */
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#define HPM_GPTMR2_BASE (0xF0088000UL)
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/* GPTMR2 base pointer */
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#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE)
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/* GPTMR3 base address */
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#define HPM_GPTMR3_BASE (0xF008C000UL)
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/* GPTMR3 base pointer */
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#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE)
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/* GPTMR4 base address */
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#define HPM_GPTMR4_BASE (0xF0090000UL)
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/* GPTMR4 base pointer */
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#define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE)
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/* GPTMR5 base address */
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#define HPM_GPTMR5_BASE (0xF0094000UL)
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/* GPTMR5 base pointer */
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#define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE)
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/* GPTMR6 base address */
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#define HPM_GPTMR6_BASE (0xF0098000UL)
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/* GPTMR6 base pointer */
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#define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE)
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/* GPTMR7 base address */
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#define HPM_GPTMR7_BASE (0xF009C000UL)
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/* GPTMR7 base pointer */
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#define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE)
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/* NTMR0 base address */
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#define HPM_NTMR0_BASE (0xF1110000UL)
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/* NTMR0 base pointer */
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#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE)
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/* PTMR base address */
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#define HPM_PTMR_BASE (0xF4120000UL)
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/* PTMR base pointer */
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#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE)
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#include "hpm_mbx_regs.h"
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/* Address of MBX instances */
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/* MBX0A base address */
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#define HPM_MBX0A_BASE (0xF00A0000UL)
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/* MBX0A base pointer */
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#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE)
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/* MBX0B base address */
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#define HPM_MBX0B_BASE (0xF00A4000UL)
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/* MBX0B base pointer */
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#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE)
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/* MBX1A base address */
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#define HPM_MBX1A_BASE (0xF00A8000UL)
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/* MBX1A base pointer */
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#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE)
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/* MBX1B base address */
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#define HPM_MBX1B_BASE (0xF00AC000UL)
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/* MBX1B base pointer */
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#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE)
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#include "hpm_ewdg_regs.h"
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/* Address of EWDG instances */
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/* EWDG0 base address */
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#define HPM_EWDG0_BASE (0xF00B0000UL)
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/* EWDG0 base pointer */
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#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE)
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/* EWDG1 base address */
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#define HPM_EWDG1_BASE (0xF00B4000UL)
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/* EWDG1 base pointer */
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#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE)
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/* PEWDG base address */
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#define HPM_PEWDG_BASE (0xF4128000UL)
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/* PEWDG base pointer */
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#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE)
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#include "hpm_dmamux_regs.h"
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/* Address of DMAMUX instances */
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/* DMAMUX base address */
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#define HPM_DMAMUX_BASE (0xF00C4000UL)
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/* DMAMUX base pointer */
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#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE)
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#include "hpm_dmav2_regs.h"
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/* Address of DMAV2 instances */
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/* HDMA base address */
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#define HPM_HDMA_BASE (0xF00C8000UL)
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/* HDMA base pointer */
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#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE)
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/* XDMA base address */
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#define HPM_XDMA_BASE (0xF3008000UL)
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/* XDMA base pointer */
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#define HPM_XDMA ((DMAV2_Type *) HPM_XDMA_BASE)
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#include "hpm_gpiom_regs.h"
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/* Address of GPIOM instances */
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/* GPIOM base address */
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#define HPM_GPIOM_BASE (0xF00D8000UL)
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/* GPIOM base pointer */
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#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE)
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#include "hpm_adc16_regs.h"
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/* Address of ADC16 instances */
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/* ADC0 base address */
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#define HPM_ADC0_BASE (0xF00E0000UL)
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/* ADC0 base pointer */
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#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE)
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#include "hpm_i2s_regs.h"
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/* Address of I2S instances */
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/* I2S0 base address */
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#define HPM_I2S0_BASE (0xF0200000UL)
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/* I2S0 base pointer */
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#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE)
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/* I2S1 base address */
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#define HPM_I2S1_BASE (0xF0204000UL)
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/* I2S1 base pointer */
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#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE)
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/* I2S2 base address */
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#define HPM_I2S2_BASE (0xF0208000UL)
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/* I2S2 base pointer */
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#define HPM_I2S2 ((I2S_Type *) HPM_I2S2_BASE)
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/* I2S3 base address */
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#define HPM_I2S3_BASE (0xF020C000UL)
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/* I2S3 base pointer */
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#define HPM_I2S3 ((I2S_Type *) HPM_I2S3_BASE)
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#include "hpm_dao_regs.h"
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/* Address of DAO instances */
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/* DAO base address */
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#define HPM_DAO_BASE (0xF0210000UL)
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/* DAO base pointer */
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#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE)
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#include "hpm_pdm_regs.h"
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/* Address of PDM instances */
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/* PDM base address */
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#define HPM_PDM_BASE (0xF0214000UL)
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/* PDM base pointer */
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#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE)
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#include "hpm_smix_regs.h"
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/* Address of SMIX instances */
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/* SMIX base address */
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#define HPM_SMIX_BASE (0xF0218000UL)
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/* SMIX base pointer */
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#define HPM_SMIX ((SMIX_Type *) HPM_SMIX_BASE)
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#include "hpm_mcan_regs.h"
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/* Address of MCAN instances */
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/* MCAN0 base address */
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#define HPM_MCAN0_BASE (0xF0280000UL)
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/* MCAN0 base pointer */
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#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE)
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/* MCAN1 base address */
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#define HPM_MCAN1_BASE (0xF0284000UL)
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/* MCAN1 base pointer */
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#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE)
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/* MCAN2 base address */
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#define HPM_MCAN2_BASE (0xF0288000UL)
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/* MCAN2 base pointer */
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#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE)
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/* MCAN3 base address */
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#define HPM_MCAN3_BASE (0xF028C000UL)
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/* MCAN3 base pointer */
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#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE)
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/* MCAN4 base address */
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#define HPM_MCAN4_BASE (0xF0290000UL)
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/* MCAN4 base pointer */
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#define HPM_MCAN4 ((MCAN_Type *) HPM_MCAN4_BASE)
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/* MCAN5 base address */
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#define HPM_MCAN5_BASE (0xF0294000UL)
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/* MCAN5 base pointer */
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#define HPM_MCAN5 ((MCAN_Type *) HPM_MCAN5_BASE)
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/* MCAN6 base address */
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#define HPM_MCAN6_BASE (0xF0298000UL)
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/* MCAN6 base pointer */
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#define HPM_MCAN6 ((MCAN_Type *) HPM_MCAN6_BASE)
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/* MCAN7 base address */
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#define HPM_MCAN7_BASE (0xF029C000UL)
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/* MCAN7 base pointer */
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#define HPM_MCAN7 ((MCAN_Type *) HPM_MCAN7_BASE)
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#include "hpm_ptpc_regs.h"
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/* Address of PTPC instances */
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/* PTPC base address */
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#define HPM_PTPC_BASE (0xF02FC000UL)
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/* PTPC base pointer */
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#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE)
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#include "hpm_lcdc_regs.h"
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/* Address of LCDC instances */
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/* LCDC base address */
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#define HPM_LCDC_BASE (0xF1000000UL)
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/* LCDC base pointer */
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#define HPM_LCDC ((LCDC_Type *) HPM_LCDC_BASE)
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/* LCDC1 base address */
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#define HPM_LCDC1_BASE (0xF1004000UL)
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/* LCDC1 base pointer */
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#define HPM_LCDC1 ((LCDC_Type *) HPM_LCDC1_BASE)
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#include "hpm_cam_regs.h"
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/* Address of CAM instances */
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/* CAM0 base address */
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#define HPM_CAM0_BASE (0xF1008000UL)
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/* CAM0 base pointer */
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#define HPM_CAM0 ((CAM_Type *) HPM_CAM0_BASE)
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/* CAM1 base address */
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#define HPM_CAM1_BASE (0xF100C000UL)
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/* CAM1 base pointer */
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#define HPM_CAM1 ((CAM_Type *) HPM_CAM1_BASE)
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#include "hpm_pdma_regs.h"
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/* Address of PDMA instances */
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/* PDMA base address */
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#define HPM_PDMA_BASE (0xF1010000UL)
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/* PDMA base pointer */
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#define HPM_PDMA ((PDMA_Type *) HPM_PDMA_BASE)
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#include "hpm_jpeg_regs.h"
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/* Address of JPEG instances */
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/* JPEG base address */
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#define HPM_JPEG_BASE (0xF1014000UL)
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/* JPEG base pointer */
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#define HPM_JPEG ((JPEG_Type *) HPM_JPEG_BASE)
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#include "hpm_gwc_regs.h"
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/* Address of GWC instances */
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/* GWC0 base address */
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#define HPM_GWC0_BASE (0xF1018000UL)
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/* GWC0 base pointer */
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#define HPM_GWC0 ((GWC_Type *) HPM_GWC0_BASE)
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/* GWC1 base address */
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#define HPM_GWC1_BASE (0xF101C000UL)
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/* GWC1 base pointer */
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#define HPM_GWC1 ((GWC_Type *) HPM_GWC1_BASE)
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#include "hpm_mipi_dsi_regs.h"
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/* Address of MIPI_DSI instances */
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/* MIPI_DSI0 base address */
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#define HPM_MIPI_DSI0_BASE (0xF1020000UL)
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/* MIPI_DSI0 base pointer */
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#define HPM_MIPI_DSI0 ((MIPI_DSI_Type *) HPM_MIPI_DSI0_BASE)
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/* MIPI_DSI1 base address */
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#define HPM_MIPI_DSI1_BASE (0xF1024000UL)
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/* MIPI_DSI1 base pointer */
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#define HPM_MIPI_DSI1 ((MIPI_DSI_Type *) HPM_MIPI_DSI1_BASE)
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#include "hpm_mipi_csi_regs.h"
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/* Address of MIPI_CSI instances */
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/* MIPI_CSI0 base address */
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#define HPM_MIPI_CSI0_BASE (0xF1028000UL)
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/* MIPI_CSI0 base pointer */
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#define HPM_MIPI_CSI0 ((MIPI_CSI_Type *) HPM_MIPI_CSI0_BASE)
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/* MIPI_CSI1 base address */
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#define HPM_MIPI_CSI1_BASE (0xF102C000UL)
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/* MIPI_CSI1 base pointer */
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#define HPM_MIPI_CSI1 ((MIPI_CSI_Type *) HPM_MIPI_CSI1_BASE)
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#include "hpm_lvb_regs.h"
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/* Address of LVB instances */
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/* LVB base address */
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#define HPM_LVB_BASE (0xF1030000UL)
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/* LVB base pointer */
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#define HPM_LVB ((LVB_Type *) HPM_LVB_BASE)
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#include "hpm_pixelmux_regs.h"
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/* Address of PIXELMUX instances */
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/* PIXEL_MUX base address */
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#define HPM_PIXEL_MUX_BASE (0xF1034000UL)
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/* PIXEL_MUX base pointer */
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#define HPM_PIXEL_MUX ((PIXELMUX_Type *) HPM_PIXEL_MUX_BASE)
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#include "hpm_lcb_regs.h"
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/* Address of LCB instances */
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/* LCB base address */
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#define HPM_LCB_BASE (0xF1038000UL)
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/* LCB base pointer */
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#define HPM_LCB ((LCB_Type *) HPM_LCB_BASE)
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#include "hpm_gpu_regs.h"
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/* Address of GPU instances */
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/* GPU base address */
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#define HPM_GPU_BASE (0xF1080000UL)
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/* GPU base pointer */
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#define HPM_GPU ((GPU_Type *) HPM_GPU_BASE)
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#include "hpm_enet_regs.h"
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/* Address of ENET instances */
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/* ENET0 base address */
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#define HPM_ENET0_BASE (0xF1100000UL)
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/* ENET0 base pointer */
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#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE)
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#include "hpm_usb_regs.h"
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/* Address of USB instances */
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/* USB0 base address */
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#define HPM_USB0_BASE (0xF1120000UL)
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/* USB0 base pointer */
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#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE)
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#include "hpm_sdxc_regs.h"
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/* Address of SDXC instances */
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/* SDXC0 base address */
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#define HPM_SDXC0_BASE (0xF1130000UL)
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/* SDXC0 base pointer */
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#define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE)
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/* SDXC1 base address */
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#define HPM_SDXC1_BASE (0xF1134000UL)
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/* SDXC1 base pointer */
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#define HPM_SDXC1 ((SDXC_Type *) HPM_SDXC1_BASE)
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#include "hpm_ddrctl_regs.h"
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/* Address of DDRCTL instances */
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/* DDRCTL base address */
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#define HPM_DDRCTL_BASE (0xF3010000UL)
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/* DDRCTL base pointer */
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#define HPM_DDRCTL ((DDRCTL_Type *) HPM_DDRCTL_BASE)
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/* Address of ROMC instances */
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/* ROMC base address */
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#define HPM_ROMC_BASE (0xF3014000UL)
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#include "hpm_ffa_regs.h"
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/* Address of FFA instances */
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/* FFA base address */
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#define HPM_FFA_BASE (0xF3018000UL)
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/* FFA base pointer */
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#define HPM_FFA ((FFA_Type *) HPM_FFA_BASE)
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#include "hpm_sdp_regs.h"
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/* Address of SDP instances */
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/* SDP base address */
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#define HPM_SDP_BASE (0xF3040000UL)
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/* SDP base pointer */
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#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE)
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#include "hpm_sec_regs.h"
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/* Address of SEC instances */
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/* SEC base address */
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#define HPM_SEC_BASE (0xF3044000UL)
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/* SEC base pointer */
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#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE)
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#include "hpm_mon_regs.h"
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/* Address of MON instances */
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/* MON base address */
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#define HPM_MON_BASE (0xF3048000UL)
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/* MON base pointer */
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#define HPM_MON ((MON_Type *) HPM_MON_BASE)
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#include "hpm_rng_regs.h"
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/* Address of RNG instances */
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/* RNG base address */
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#define HPM_RNG_BASE (0xF304C000UL)
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/* RNG base pointer */
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#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE)
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#include "hpm_otp_regs.h"
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/* Address of OTP instances */
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/* OTP base address */
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#define HPM_OTP_BASE (0xF3050000UL)
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/* OTP base pointer */
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#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE)
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#include "hpm_keym_regs.h"
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/* Address of KEYM instances */
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/* KEYM base address */
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#define HPM_KEYM_BASE (0xF3054000UL)
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/* KEYM base pointer */
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#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE)
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#include "hpm_sysctl_regs.h"
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/* Address of SYSCTL instances */
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/* SYSCTL base address */
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#define HPM_SYSCTL_BASE (0xF4000000UL)
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/* SYSCTL base pointer */
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#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE)
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#include "hpm_ioc_regs.h"
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/* Address of IOC instances */
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/* IOC base address */
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#define HPM_IOC_BASE (0xF4040000UL)
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/* IOC base pointer */
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#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE)
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/* PIOC base address */
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#define HPM_PIOC_BASE (0xF4118000UL)
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/* PIOC base pointer */
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#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE)
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/* BIOC base address */
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#define HPM_BIOC_BASE (0xF4210000UL)
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/* BIOC base pointer */
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#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE)
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#include "hpm_pllctlv2_regs.h"
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/* Address of PLLCTLV2 instances */
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/* PLLCTLV2 base address */
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#define HPM_PLLCTLV2_BASE (0xF40C0000UL)
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/* PLLCTLV2 base pointer */
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#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE)
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#include "hpm_ppor_regs.h"
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/* Address of PPOR instances */
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/* PPOR base address */
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#define HPM_PPOR_BASE (0xF4100000UL)
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/* PPOR base pointer */
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#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE)
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#include "hpm_pcfg_regs.h"
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/* Address of PCFG instances */
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/* PCFG base address */
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#define HPM_PCFG_BASE (0xF4104000UL)
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/* PCFG base pointer */
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#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE)
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#include "hpm_pgpr_regs.h"
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/* Address of PGPR instances */
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/* PGPR0 base address */
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#define HPM_PGPR0_BASE (0xF4110000UL)
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/* PGPR0 base pointer */
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#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE)
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/* PGPR1 base address */
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#define HPM_PGPR1_BASE (0xF4114000UL)
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/* PGPR1 base pointer */
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#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE)
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#include "hpm_vad_regs.h"
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/* Address of VAD instances */
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/* VAD base address */
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#define HPM_VAD_BASE (0xF412C000UL)
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/* VAD base pointer */
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#define HPM_VAD ((VAD_Type *) HPM_VAD_BASE)
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#include "hpm_mipi_dsi_phy_regs.h"
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/* Address of MIPI_DSI_PHY instances */
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/* MIPI_DSI_PHY0 base address */
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#define HPM_MIPI_DSI_PHY0_BASE (0xF4140000UL)
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/* MIPI_DSI_PHY0 base pointer */
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#define HPM_MIPI_DSI_PHY0 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY0_BASE)
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/* MIPI_DSI_PHY1 base address */
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#define HPM_MIPI_DSI_PHY1_BASE (0xF4144000UL)
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/* MIPI_DSI_PHY1 base pointer */
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#define HPM_MIPI_DSI_PHY1 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY1_BASE)
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#include "hpm_mipi_csi_phy_regs.h"
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/* Address of MIPI_CSI_PHY instances */
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/* MIPI_CSI_PHY0 base address */
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#define HPM_MIPI_CSI_PHY0_BASE (0xF4148000UL)
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/* MIPI_CSI_PHY0 base pointer */
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#define HPM_MIPI_CSI_PHY0 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY0_BASE)
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/* MIPI_CSI_PHY1 base address */
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#define HPM_MIPI_CSI_PHY1_BASE (0xF414C000UL)
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/* MIPI_CSI_PHY1 base pointer */
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#define HPM_MIPI_CSI_PHY1 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY1_BASE)
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#include "hpm_ddrphy_regs.h"
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/* Address of DDRPHY instances */
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/* DDRPHY base address */
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#define HPM_DDRPHY_BASE (0xF4150000UL)
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/* DDRPHY base pointer */
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#define HPM_DDRPHY ((DDRPHY_Type *) HPM_DDRPHY_BASE)
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#include "hpm_tsns_regs.h"
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/* Address of TSNS instances */
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/* TSNS base address */
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#define HPM_TSNS_BASE (0xF4154000UL)
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/* TSNS base pointer */
|
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#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE)
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#include "hpm_bacc_regs.h"
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/* Address of BACC instances */
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/* BACC base address */
|
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#define HPM_BACC_BASE (0xF4200000UL)
|
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/* BACC base pointer */
|
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#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE)
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#include "hpm_bpor_regs.h"
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/* Address of BPOR instances */
|
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/* BPOR base address */
|
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#define HPM_BPOR_BASE (0xF4204000UL)
|
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/* BPOR base pointer */
|
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#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE)
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#include "hpm_bcfg_regs.h"
|
|
/* Address of BCFG instances */
|
|
/* BCFG base address */
|
|
#define HPM_BCFG_BASE (0xF4208000UL)
|
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/* BCFG base pointer */
|
|
#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE)
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|
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#include "hpm_butn_regs.h"
|
|
/* Address of BUTN instances */
|
|
/* BUTN base address */
|
|
#define HPM_BUTN_BASE (0xF420C000UL)
|
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/* BUTN base pointer */
|
|
#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE)
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|
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#include "hpm_bgpr_regs.h"
|
|
/* Address of BGPR instances */
|
|
/* BGPR base address */
|
|
#define HPM_BGPR_BASE (0xF4218000UL)
|
|
/* BGPR base pointer */
|
|
#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE)
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|
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#include "hpm_rtc_regs.h"
|
|
/* Address of RTC instances */
|
|
/* RTCSHW base address */
|
|
#define HPM_RTCSHW_BASE (0xF421C000UL)
|
|
/* RTCSHW base pointer */
|
|
#define HPM_RTCSHW ((RTC_Type *) HPM_RTCSHW_BASE)
|
|
/* RTC base address */
|
|
#define HPM_RTC_BASE (0xF4244000UL)
|
|
/* RTC base pointer */
|
|
#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE)
|
|
|
|
#include "hpm_bsec_regs.h"
|
|
/* Address of BSEC instances */
|
|
/* BSEC base address */
|
|
#define HPM_BSEC_BASE (0xF4240000UL)
|
|
/* BSEC base pointer */
|
|
#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE)
|
|
|
|
#include "hpm_bkey_regs.h"
|
|
/* Address of BKEY instances */
|
|
/* BKEY base address */
|
|
#define HPM_BKEY_BASE (0xF4248000UL)
|
|
/* BKEY base pointer */
|
|
#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE)
|
|
|
|
#include "hpm_bmon_regs.h"
|
|
/* Address of BMON instances */
|
|
/* BMON base address */
|
|
#define HPM_BMON_BASE (0xF424C000UL)
|
|
/* BMON base pointer */
|
|
#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE)
|
|
|
|
#include "hpm_tamp_regs.h"
|
|
/* Address of TAMP instances */
|
|
/* TAMP base address */
|
|
#define HPM_TAMP_BASE (0xF4250000UL)
|
|
/* TAMP base pointer */
|
|
#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE)
|
|
|
|
#include "hpm_mono_regs.h"
|
|
/* Address of MONO instances */
|
|
/* MONO base address */
|
|
#define HPM_MONO_BASE (0xF4254000UL)
|
|
/* MONO base pointer */
|
|
#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE)
|
|
|
|
|
|
#include "riscv/riscv_core.h"
|
|
#include "hpm_csr_regs.h"
|
|
#include "hpm_interrupt.h"
|
|
#include "hpm_misc.h"
|
|
#include "hpm_dmamux_src.h"
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#include "hpm_iomux.h"
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#include "hpm_pmic_iomux.h"
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#include "hpm_batt_iomux.h"
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#endif /* HPM_SOC_H */
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