370 lines
12 KiB
C
370 lines
12 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-14 wangqiang the first version
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*/
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#include <rtthread.h>
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#ifdef PHY_USING_KSZ8081
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#include <rtdevice.h>
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#include "drv_gpio.h"
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#include "drv_mdio.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the PHY registers. */
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#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
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#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
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#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
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#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
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#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
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#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
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#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
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/*! @brief Defines the mask flag in basic control register. */
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#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
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#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
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#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
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#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
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#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
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#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
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#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
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/*!@brief Defines the mask flag of operation mode in control two register*/
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#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
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#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
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#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
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#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
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#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
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#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
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#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
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#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
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#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
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#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
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/*! @brief Defines the mask flag in basic status register. */
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#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
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#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
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#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
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/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
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#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
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#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
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#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
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#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
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#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
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/*! @brief Defines the timeout macro. */
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#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
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/* defined the Reset pin, PORT and PIN config by menuconfig */
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#define RESET_PIN GET_PIN(PHY_RESET_PORT, PHY_RESET_PIN)
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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static struct rt_phy_device phy_ksz8081;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static inline rt_bool_t read_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t *value)
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{
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if (4 != bus->ops->read(bus, addr, reg_id, value, 4))
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{
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return RT_FALSE;
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}
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return RT_TRUE;
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}
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static inline rt_bool_t write_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t value)
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{
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if (4 != bus->ops->write(bus, addr, reg_id, &value, 4))
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{
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return RT_FALSE;
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}
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return RT_TRUE;
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}
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static rt_phy_status rt_phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz)
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{
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rt_bool_t ret;
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rt_phy_status result;
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rt_uint32_t counter = PHY_TIMEOUT_COUNT;
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rt_uint32_t id_reg = 0;
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rt_uint32_t time_delay;
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rt_uint32_t bss_reg;
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rt_uint32_t ctl_reg = 0;
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// reset phy device by gpio
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rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
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rt_pin_write(RESET_PIN, PIN_LOW);
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rt_thread_mdelay(100);
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rt_pin_write(RESET_PIN, PIN_HIGH);
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rt_mdio_t *mdio_bus = rt_hw_mdio_register(object, "phy_mdio");
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if (RT_NULL == mdio_bus)
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{
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return PHY_STATUS_FAIL;
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}
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phy_ksz8081.bus = mdio_bus;
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phy_ksz8081.addr = phy_addr;
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ret = mdio_bus->ops->init(mdio_bus, src_clock_hz);
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if ( !ret )
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{
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return PHY_STATUS_FAIL;
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}
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/* Initialization after PHY stars to work. */
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while ((id_reg != PHY_CONTROL_ID1) && (counter != 0))
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{
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phy_ksz8081.ops->read(PHY_ID1_REG, &id_reg);
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counter--;
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}
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if (!counter)
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{
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return PHY_STATUS_FAIL;
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}
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/* Reset PHY. */
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counter = PHY_TIMEOUT_COUNT;
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result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (PHY_STATUS_OK == result)
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{
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#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
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rt_uint32_t data = 0;
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result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data);
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if (PHY_STATUS_FAIL == result)
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{
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return PHY_STATUS_FAIL;
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}
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result = phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
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if (PHY_STATUS_FAIL == result)
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{
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return PHY_STATUS_FAIL;
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}
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#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
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/* Set the negotiation. */
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result = phy_ksz8081.ops->write(PHY_AUTONEG_ADVERTISE_REG,
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(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
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PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
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if (PHY_STATUS_OK == result)
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{
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result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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if (PHY_STATUS_OK == result)
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{
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/* Check auto negotiation complete. */
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while (counter--)
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{
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result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &bss_reg);
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if (PHY_STATUS_OK == result)
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{
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phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg);
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if (((bss_reg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctl_reg & PHY_LINK_READY_MASK))
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{
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/* Wait a moment for Phy status stable. */
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for (time_delay = 0; time_delay < PHY_TIMEOUT_COUNT; time_delay++)
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{
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__ASM("nop");
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}
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break;
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}
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}
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if (!counter)
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{
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return PHY_STATUS_FAIL;
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}
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}
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}
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}
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}
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return PHY_STATUS_OK;
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}
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static rt_phy_status rt_phy_read(rt_uint32_t reg, rt_uint32_t *data)
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{
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rt_mdio_t *mdio_bus = phy_ksz8081.bus;
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rt_uint32_t device_id = phy_ksz8081.addr;
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if (read_reg(mdio_bus, device_id, reg, data))
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{
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return PHY_STATUS_OK;
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}
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return PHY_STATUS_FAIL;
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}
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static rt_phy_status rt_phy_write(rt_uint32_t reg, rt_uint32_t data)
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{
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rt_mdio_t *mdio_bus = phy_ksz8081.bus;
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rt_uint32_t device_id = phy_ksz8081.addr;
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if (write_reg(mdio_bus, device_id, reg, data))
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{
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return PHY_STATUS_OK;
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}
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return PHY_STATUS_FAIL;
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}
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static rt_phy_status rt_phy_loopback(rt_uint32_t mode, rt_uint32_t speed, rt_bool_t enable)
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{
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rt_uint32_t data = 0;
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rt_phy_status result;
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/* Set the loop mode. */
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if (enable)
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{
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if (PHY_LOCAL_LOOP == mode)
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{
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if (PHY_SPEED_100M == speed)
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{
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data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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else
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{
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data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, data);
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}
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else
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{
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/* First read the current status in control register. */
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result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data);
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if (PHY_STATUS_OK == result)
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{
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return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
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}
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}
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}
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else
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{
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/* Disable the loop mode. */
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if (PHY_LOCAL_LOOP == mode)
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{
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/* First read the current status in control register. */
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result = phy_ksz8081.ops->read(PHY_BASICCONTROL_REG, &data);
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if (PHY_STATUS_OK == result)
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{
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data &= ~PHY_BCTL_LOOP_MASK;
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return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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else
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{
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/* First read the current status in control one register. */
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result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data);
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if (PHY_STATUS_OK == result)
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{
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return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
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}
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}
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}
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return result;
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}
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static rt_phy_status get_link_status(rt_bool_t *status)
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{
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rt_phy_status result;
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rt_uint32_t data;
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/* Read the basic status register. */
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result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &data);
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if (PHY_STATUS_OK == result)
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{
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if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
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{
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/* link down. */
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*status = RT_FALSE;
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}
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else
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{
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/* link up. */
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*status = RT_TRUE;
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}
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}
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return result;
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}
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static rt_phy_status get_link_speed_duplex(rt_uint32_t *speed, rt_uint32_t *duplex)
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{
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rt_phy_status result = PHY_STATUS_OK;
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rt_uint32_t data, ctl_reg;
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/* Read the control two register. */
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result = phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg);
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if (PHY_STATUS_OK == result)
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{
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data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
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{
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/* Full duplex. */
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*duplex = PHY_FULL_DUPLEX;
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}
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else
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{
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/* Half duplex. */
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*duplex = PHY_HALF_DUPLEX;
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}
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data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
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{
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/* 100M speed. */
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*speed = PHY_SPEED_100M;
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}
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else
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{ /* 10M speed. */
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*speed = PHY_SPEED_10M;
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}
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}
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return result;
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}
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static struct rt_phy_ops phy_ops =
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{
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.init = rt_phy_init,
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.read = rt_phy_read,
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.write = rt_phy_write,
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.loopback = rt_phy_loopback,
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.get_link_status = get_link_status,
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.get_link_speed_duplex = get_link_speed_duplex,
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};
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static int rt_phy_ksz8081_register( void )
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{
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phy_ksz8081.ops = &phy_ops;
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rt_hw_phy_register(&phy_ksz8081, "rtt-phy");
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return 1;
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}
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INIT_DEVICE_EXPORT(rt_phy_ksz8081_register);
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#endif /* PHY_USING_KSZ8081 */
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