169 lines
6.0 KiB
C
169 lines
6.0 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fpcie_dma.c
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* Date: 2022-08-10 14:55:11
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* LastEditTime: 2022-08-18 08:57:38
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* Description: This file is for pcie dma implementation.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 huanghe 2022/8/18 init commit
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*/
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#include "fpcie_hw.h"
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#include "fpcie_dma.h"
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#include "fpcie.h"
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#include "ftypes.h"
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#include "fcache.h"
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#include "fkernel.h"
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#include "fdebug.h"
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/***************************** Include Files *********************************/
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/************************** Variable Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FPCIE_DMA_DEBUG_TAG "FPCIE_DMA"
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#define FPCIE_DMA_ERROR(format, ...) FT_DEBUG_PRINT_E(FPCIE_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPCIE_DMA_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FPCIE_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPCIE_DMA_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FPCIE_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FPCIE_DMA_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FPCIE_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Function Prototypes ******************************/
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/**
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* @name: FPcieDmaDescSet
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* @msg: PCIE DMA descriptor group packet
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* @param {uintptr} axi_addr is memory address
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* @param {uintptr} bar_addr is Base Address Register value
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* @param {u32} length want to send byte length
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* @param {struct FPcieDmaDescriptor *} desc Desc is the descriptor to be configured
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* @param {struct FPcieDmaDescriptor *} next_desc is the next descriptor that needs to be sent
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* @return {FError}
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*/
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FError FPcieDmaDescSet(uintptr axi_addr,
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uintptr bar_addr,
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u32 length,
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struct FPcieDmaDescriptor *desc,
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struct FPcieDmaDescriptor *next_desc)
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{
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/* 设置内存地址 */
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desc->axi_base_address = axi_addr;
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desc->axi_address_phase_controls = 0x00;
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/* 设置pcie空间地址 */
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desc->pcie_base_address = bar_addr;
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desc->pcie_tlp_header_attributes = 0x01;
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/* 设置数据长度， 设置dma完成中断 */
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desc->transfer_control = length;
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desc->axi_bus_status = 0x00;
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desc->pcie_bus_status = 0x00;
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desc->channel_status = 0x00;
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if (next_desc != NULL)
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{
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/* 使能链表模式 */
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desc->transfer_control &= ~(BIT(24));
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desc->transfer_control |= BIT(29);
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/* 设置下一级链表地址 */
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desc->next_descriptor = (uintptr)next_desc;
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}
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else
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{
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desc->transfer_control |= BIT(24);
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desc->transfer_control &= ~(BIT(29));
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desc->next_descriptor = 0;
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}
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return 0;
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}
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/**
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* @name: FPcieDmaRead
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* @msg: Pcie reads through dma
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* @param {uintptr} bar_addr is Base Address Register value
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* @param {FPcieDmaDescriptor} *desc is first address of the receive descriptor
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*/
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void FPcieDmaRead(uintptr bar_address, struct FPcieDmaDescriptor *desc)
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{
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/* The enable channel is interrupted */
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_INT_ENABLE_OFFSET, FPCIE_CTRL_DMA_INT_ENABLE_CH0_DONE_MASK | FPCIE_CTRL_DMA_INT_ENABLE_CH0_ERR_MASK);
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH0_SP_L_OFFSET, (u32)((uintptr)desc & 0xffffffffU));
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#ifdef __aarch64__
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH0_SP_H_OFFSET, (u32)(((uintptr)desc >> 32) & 0xffffffffU));
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#else
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH0_SP_H_OFFSET, 0);
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#endif
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH0_CTRL_OFFSET, FPCIE_CTRL_DMA_CH0_CTRL_GO_MASK);
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}
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/**
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* @name: FPcieDmaWrite
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* @msg: Pcie writes through dma
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* @param {uintptr} bar_address is Base Address Register value
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* @param {FPcieDmaDescriptor} *desc is first address of the send descriptor
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*/
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void FPcieDmaWrite(uintptr bar_address, struct FPcieDmaDescriptor *desc)
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{
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/* The enable channel is interrupted */
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_INT_ENABLE_OFFSET, FPCIE_CTRL_DMA_INT_ENABLE_CH1_DONE_MASK | FPCIE_CTRL_DMA_INT_ENABLE_CH1_ERR_MASK);
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH1_SP_L_OFFSET, (u32)((uintptr)desc & 0xffffffffU));
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#ifdef __aarch64__
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH1_SP_H_OFFSET, (u32)(((uintptr)desc >> 32) & 0xffffffffU));
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#else
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH1_SP_H_OFFSET, 0);
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#endif
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FPCIE_WRITEREG(bar_address, FPCIE_REG_DMA_CH1_CTRL_OFFSET, FPCIE_CTRL_DMA_CH1_CTRL_GO_MASK | FPCIE_CTRL_DMA_CH1_CTRL_OBNOTIB_MASK);
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}
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/**
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* @name: FPcieDmaPollDone
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* @msg: Polling waits for DMA to complete
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* @param {FPcieDmaDescriptor *} desc is the current need to wait for dma to complete
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* @param {u32} wait_cnt is the count that needs to wait to end
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* @return FError
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*/
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FError FPcieDmaPollDone(struct FPcieDmaDescriptor *desc, u32 wait_cnt)
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{
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FPCIE_DMA_DEBUG_I("Desc axi_bus_status :[0x%02x].", desc->axi_bus_status);
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FPCIE_DMA_DEBUG_I("Desc pcie_bus_status:[0x%02x].", desc->pcie_bus_status);
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FPCIE_DMA_DEBUG_I("Desc channel_status :[0x%02x].", desc->channel_status);
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while (wait_cnt > 0)
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{
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if (desc->channel_status == 0x1)
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{
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FPCIE_DMA_DEBUG_I("Dma channel transfer done.");
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return FT_SUCCESS;
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}
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wait_cnt--;
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}
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return FPCIE_ERR_TIMEOUT;
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}
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