676 lines
22 KiB
C
676 lines
22 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fgic.c
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* Date: 2022-03-28 09:30:23
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* LastEditTime: 2022-03-28 09:30:24
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* Description: This file is for the minimum required function implementations for this driver.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 huanghe 2022/4/16 init commit
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*/
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#include "fgic.h"
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#include "fgic_distributor.h"
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#include "fgic_cpu_interface.h"
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#include "fgic_redistributor.h"
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#include "fgic_hw.h"
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#include "ftypes.h"
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#include "fkernel.h"
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#include "fassert.h"
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#include "fdebug.h"
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#define FGIC_DEBUG_TAG "FGIC"
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#define FGIC_ERROR(format, ...) FT_DEBUG_PRINT_E(FGIC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGIC_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FGIC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGIC_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FGIC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGIC_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FGIC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FGIC_SPI_START_ID 32
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#define FGIC_PPI_END_ID 31
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#define FGIC_SGI_END_ID 15
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#define FGIC_GICD_32_PER_REG 32
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#define FGIC_GICD_16_PER_REG 16
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#define FGIC_GICD_4_PER_REG 4
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#define FGIC_INT_DEFAULT_PRI_X4 0xa0a0a0a0 /* 考虑到当前一般程序工作于EL1，对于NS 或 S 安全状态 ，0x80 - 0xff 的优先级都有存在的可能性 */
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#define FGIC_CPU_INTERFACE_DEFAULT_FLITER 0xFF
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typedef enum
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{
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GICD_CTLR_RWP_WAIT = 0, /* Use GICD_CTLR for test */
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GICR_CTLR_RWP_WAIT, /* Use GICR_CTLR for test */
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} WAIT_RWP_MODE;
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/**
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* @name: FGicWaitRwp
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* @msg: Wait for register write pending
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* @param {uintptr} ctrl_base is a GICD_CTLR address
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* @param {WAIT_RWP_MODE} wait_mode
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* @return {*}
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*/
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static FError FGicWaitRwp(uintptr ctrl_base, WAIT_RWP_MODE wait_mode)
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{
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u32 rwp_mask;
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u32 timeout_cnt = 0;
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if (GICD_CTLR_RWP_WAIT == wait_mode)
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{
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rwp_mask = FGIC_GICD_CTLR_RWP_MASK;
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}
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else if (GICR_CTLR_RWP_WAIT == wait_mode)
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{
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rwp_mask = FGIC_GICR_CTLR_RWP_MASK;
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}
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else
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{
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FGIC_DEBUG_E(" wait_mode not in WAIT_RWP_MODE.");
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return FGIC_CTLR_ERR_TYPE;
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}
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while (FGIC_READREG32(ctrl_base, 0) & rwp_mask)
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{
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if (timeout_cnt ++ >= 0xffffff)
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{
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FGIC_DEBUG_E(" Wait rwp timeout.");
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return FGIC_CTLR_ERR_IN_GET;
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}
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}
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return FGIC_SUCCESS;
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}
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/**
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* @name: void FGicDistrubutiorInit(FGic *instance_p)
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* @msg: Initialize Distrubutior
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* @param {FGic} *instance_p is a pointer to the FGic instance.
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*/
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void FGicDistrubutiorInit(FGic *instance_p)
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{
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FASSERT(instance_p);
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FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
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u32 max_ints_mun, int_id, int_index;
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uintptr dis_base = instance_p->config.dis_base;
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max_ints_mun = instance_p->max_spi_num;
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/* Disable the distributor */
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FGIC_WRITEREG32(dis_base, FGIC_GICD_CTLR_OFFSET, 0);
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FASSERT(FGicWaitRwp(dis_base + FGIC_GICD_CTLR_OFFSET, GICD_CTLR_RWP_WAIT) == FGIC_SUCCESS);
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if (instance_p->security == ONE_NS_SECURITY_STATE)
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{
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/* Make GICD_CTLR.DS = 1 ,Non-secure accesses are permitted to access and modify registers that control Group 0 interrupts */
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FGIC_SETBIT(dis_base, FGIC_GICD_CTLR_OFFSET, FGIC_GICD_CTLR_DS_MASK);
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FASSERT(FGIC_READREG32(dis_base, FGIC_GICD_CTLR_OFFSET) & FGIC_GICD_CTLR_DS_MASK);
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}
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/* 关闭所有中断，并将中断分组默认为group 1 */
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for (int_id = FGIC_SPI_START_ID; int_id < max_ints_mun; int_id += FGIC_GICD_32_PER_REG)
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{
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int_index = int_id / FGIC_GICD_32_PER_REG;
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/* Disables forwarding of the corresponding interrupt. */
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FGIC_GICD_ICENABLER_WRITE_N_MASK(dis_base, int_id, FGIC_GICD_ICENABLER_DEFAULT_MASK);
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/* Changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. */
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FGIC_GICD_ICPENDR_WRITE_N_MASK(dis_base, int_id, FGIC_GICD_ICPENDR_DEFAULT_MASK);
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if (instance_p->security == ONE_NS_SECURITY_STATE)
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{
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FGIC_GICD_IGROUPR_WRITE_N_MASK(dis_base, int_id, FGIC_GICD_ICPENDR_DEFAULT_MASK);
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}
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else
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{
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FGIC_GICD_IGROUPR_WRITE_N_MASK(dis_base, int_id, FGIC_GICD_ICPENDR_DEFAULT_MASK);
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}
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FGIC_GICD_IGRPMODR_WRITE_N_MASK(dis_base, int_id, FGIC_GICD_IGRPMODR_DEFAULT_MASK);
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}
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FASSERT(FGicWaitRwp(dis_base + FGIC_GICD_CTLR_OFFSET, GICD_CTLR_RWP_WAIT) == FGIC_SUCCESS);
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for (int_id = FGIC_SPI_START_ID; int_id < max_ints_mun; int_id += FGIC_GICD_4_PER_REG)
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{
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FGIC_GICD_IPRIORITYR_WRITE_N_MASK(dis_base, int_id, FGIC_INT_DEFAULT_PRI_X4);
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}
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for (int_id = FGIC_SPI_START_ID; int_id < max_ints_mun; int_id += FGIC_GICD_16_PER_REG)
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{
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FGIC_GICD_ICFGR_WRITE_N_MASK(dis_base, int_id, 0); /* level-sensitive */
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}
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if (instance_p->security == ONE_NS_SECURITY_STATE)
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{
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FGIC_GICD_CTLR_WRITE(dis_base, GICD_CTLR_BIT_ARE_S | GICD_CTLR_ENABLE_GRP1_NS);
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}
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else
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{
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FGIC_GICD_CTLR_WRITE(dis_base, GICD_CTLR_BIT_ARE_NS | GICD_CTLR_ENABLE_GRP1_NS);
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}
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}
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/**
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* @name: FError FGicRedistrubutiorInit(FGic *instance_p)
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* @msg: Initialize Redistrubutior
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* @param {FGic} *instance_p is a pointer to the FGic instance.
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* @return {FError} FGIC_SUCCESS is success ,FGIC_ERR_IN_TIMEOUT is timeout
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*/
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FError FGicRedistrubutiorInit(FGic *instance_p)
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{
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FASSERT(instance_p);
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FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
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s32 int_id ;
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u32 timeout = 0;
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uintptr redis_base = instance_p->redis_base;
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uintptr sgi_base = instance_p->redis_base + FGIC_GICR_SGI_BASE_OFFSET;
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/* Clear processor sleep and wait till childasleep is cleard */
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FGIC_GICR_WAKER_CLEAR_BIT(redis_base, FGIC_GICR_WAKER_PROCESSOR_SLEEP_MASK);
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while (FGIC_GICR_WAKER_READ(redis_base) & FGIC_GICR_WAKER_CHILDREN_ASLEEP_MASK)
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{
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timeout++;
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if (timeout >= 0xfffffff)
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{
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return FGIC_ERR_IN_TIMEOUT;
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}
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}
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FASSERT(FGicWaitRwp(redis_base, GICR_CTLR_RWP_WAIT) == FGIC_SUCCESS);
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FGIC_GICR_ICENABLER0_WRITE(sgi_base, FGIC_GICR_ICENABLER0_DEFAULT_MASK); /* Disable all sgi ppi */
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/* Clear pending */
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FGIC_GICR_ICPENDR0_WRITE(sgi_base, FGIC_GICR_ICPENDR0_DEFAULT_MASK);
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/* Set sgi ppi route to different security group */
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if (instance_p->security == ONE_NS_SECURITY_STATE)
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{
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FGIC_GICR_IGROUPR0_WRITE(sgi_base, FGIC_GICR_IGROUPR0_DEFAULT_MASK);
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}
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else
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{
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FGIC_GICR_IGROUPR0_WRITE(sgi_base, FGIC_GICR_IGROUPR0_DEFAULT_MASK);
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}
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FGIC_GICR_IGRPMODR0_WRITE(sgi_base, FGIC_GICR_IGRPMODR0_DEFAULT_MASK);
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/* 默认所有优先级为0xa0 */
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for (int_id = 0; int_id < FGIC_SPI_START_ID; int_id += FGIC_GICD_4_PER_REG)
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{
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FGIC_GICR_IPRIORITYR_WRITE(sgi_base, int_id, FGIC_INT_DEFAULT_PRI_X4);
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}
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FGIC_GICR_ICFGR0_WRITE(sgi_base, 0); /* set level-sensitive */
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FGIC_GICR_ICFGR1_WRITE(sgi_base, 0);
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return FGIC_SUCCESS;
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}
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/**
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* @name: void FGicCpuInterfaceInit(void)
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* @msg: Initialize Cpu interface of current core
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*/
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void FGicCpuInterfaceInit(void)
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{
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u32 reg;
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reg = FGicGetICC_SRE_EL1();
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if (!(reg & GICC_SRE_SRE))
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{
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reg |= (GICC_SRE_SRE | GICC_SRE_DFB | GICC_SRE_DIB);
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FGicSetICC_SRE_EL1(reg);
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reg = FGicGetICC_SRE_EL1();
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FASSERT(reg & GICC_SRE_SRE);
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}
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FGicSetICC_PMR(FGIC_CPU_INTERFACE_DEFAULT_FLITER);
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FGicEnableGroup1_EL1();
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FGicSetICC_CTLR_EL1(GICC_CTLR_CBPR); /* ICC_BPR0_EL1 determines the preemption group for both Group 0 and Group 1 interrupts. */
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}
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/**
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* @name: FError FGicCfgInitialize(FGic *instance_p, const FGicConfig *input_config_p , uintptr redis_base)
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* @msg: Initialize the GIC driver instance based on the incoming configuration
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* @param {FGic} *instance_p is a pointer to the FGic instance.
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* @param {FGicConfig} *input_config_p Configuration items that need to be applied in the instance
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* @param {uintptr} redis_base is the redistributor adress of current core
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* @return {*}
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*/
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FError FGicCfgInitialize(FGic *instance_p, const FGicConfig *input_config_p, uintptr redis_base)
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{
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u32 max_ints_mun;
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uintptr dis_base;
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FASSERT(instance_p && input_config_p);
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instance_p->config = *input_config_p;
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instance_p->redis_base = redis_base ;
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instance_p->is_ready = FT_COMPONENT_IS_READY;
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dis_base = instance_p->config.dis_base;
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max_ints_mun = FGIC_READREG32(dis_base, FGIC_GICD_TYPER_OFFSET);
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max_ints_mun &= FGIC_GICD_TYPER_ITLINESNUMBER_MASK ;
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max_ints_mun = ((max_ints_mun + 1) << 5) - 1; /* If the value of this field is N, the maximum SPI INTID is 32(N+1) minus 1. */
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instance_p->max_spi_num = max_ints_mun;
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return FGIC_SUCCESS;
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}
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/**
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* @name: FError FGicIntEnable(FGic *instance_p,s32 int_id)
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* @msg: Enables the interrupt function based on the interrupt number
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* @param {FGic} *instance_p is a pointer to the FGic instance.
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* @param {s32} int_id is interrupt id
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* @return {*}
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*/
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FError FGicIntEnable(FGic *instance_p, s32 int_id)
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{
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FASSERT(instance_p);
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FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
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if (int_id > instance_p->max_spi_num)
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{
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FGIC_DEBUG_E("int_id is over max spi num for FGicIntEnable.");
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return FGIC_CTLR_ERR_NUM;
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}
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if (int_id <= FGIC_PPI_END_ID)
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{
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uintptr redis_base = instance_p->redis_base;
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FGicEnablePrivateInt(redis_base, int_id);
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}
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else
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{
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uintptr dis_base = instance_p->config.dis_base;
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FGicEnableSPI(dis_base, int_id);
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}
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return FGIC_SUCCESS ;
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}
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/**
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* @name: FError FGicIntEnable(FGic *instance_p,s32 int_id)
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* @msg: Disable the interrupt function based on the interrupt number
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* @param {FGic} *instance_p is a pointer to the FGic instance.
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* @param {s32} int_id is interrupt id
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*/
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FError FGicIntDisable(FGic *instance_p, s32 int_id)
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{
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FASSERT(instance_p);
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FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
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if (int_id > instance_p->max_spi_num)
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{
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FGIC_DEBUG_E("int_id is over max spi num for FGicIntDisable.");
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return FGIC_CTLR_ERR_NUM;
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}
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if (int_id <= FGIC_PPI_END_ID)
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{
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uintptr redis_base = instance_p->redis_base;
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FGicDisablePrivateInt(redis_base, int_id);
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}
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else
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{
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uintptr dis_base = instance_p->config.dis_base;
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FGicDisableSPI(dis_base, int_id);
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}
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return FGIC_SUCCESS ;
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}
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/**
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* @name: FError FGicSetPriority(FGic *instance_p,s32 int_id,u32 priority)
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* @msg: Sets the current interrupt priority value based on the interrupt number
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* @param {FGic} *instance_p is a pointer to the FGic instance.
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* @param {s32} int_id is interrupt id
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* @param {u32} priority is priority value ,valid bit is bit[0:7]
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* @return {*}
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*/
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FError FGicSetPriority(FGic *instance_p, s32 int_id, u32 priority)
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{
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FASSERT(instance_p);
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FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
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if (int_id > instance_p->max_spi_num)
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{
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FGIC_DEBUG_E("int_id is over max spi num for FGicSetPriority.");
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return FGIC_CTLR_ERR_IN_GET;
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}
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if (int_id <= FGIC_PPI_END_ID)
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{
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uintptr redis_base = instance_p->redis_base;
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FGicSetPrivatePriority(redis_base, int_id, priority);
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}
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else
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{
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uintptr dis_base = instance_p->config.dis_base;
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FGicSetSpiPriority(dis_base, int_id, priority);
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}
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return FGIC_SUCCESS ;
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}
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/**
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* @name: u32 FGicGetPriority(FGic *instance_p,s32 int_id)
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* @msg: Gets the current interrupt priority value based on the interrupt number
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* @param {FGic} *instance_p is a pointer to the FGic instance
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* @param {s32} int_id is interrupt id
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* @return {u32} priority value ,valid bit is bit[0:7]
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*/
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u32 FGicGetPriority(FGic *instance_p, s32 int_id)
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{
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u32 priority;
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FASSERT(instance_p);
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FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
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if (int_id > instance_p->max_spi_num)
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{
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FGIC_DEBUG_E("int_id is over max spi num for FGicGetPriority.");
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return (u32)FGIC_CTLR_ERR_IN_GET;
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}
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if (int_id <= FGIC_PPI_END_ID)
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{
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uintptr redis_base = instance_p->redis_base;
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priority = FGicGetPrivatePriority(redis_base, int_id);
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}
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else
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{
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uintptr dis_base = instance_p->config.dis_base;
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priority = FGicGetSpiPriority(dis_base, int_id);
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}
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return priority ;
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}
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/**
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* @name: FError FGicSetTriggerLevel(FGic *instance_p,s32 int_id,TRIGGER_LEVEL trigger_way)
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* @msg: Sets the interrupt triggering mode based on the current interrupt number
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* @param {FGic} *instance_p is a pointer to the FGic instance
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* @param {s32} int_id is interrupt id
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* @param {TRIGGER_LEVEL} trigger_way is trigger mode
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* @return {*}
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*/
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FError FGicSetTriggerLevel(FGic *instance_p, s32 int_id, TRIGGER_LEVEL trigger_way)
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{
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FASSERT(instance_p);
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FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
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if (int_id > instance_p->max_spi_num)
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{
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FGIC_DEBUG_E("int_id is over max spi num for FGicSetTriggerLevel.");
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return FGIC_CTLR_ERR_IN_SET;
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}
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if (int_id <= FGIC_SGI_END_ID)
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{
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uintptr redis_base = instance_p->redis_base;
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FGicSetSgiLevel(redis_base, int_id, trigger_way);
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}
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else if (int_id <= FGIC_PPI_END_ID)
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{
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uintptr redis_base = instance_p->redis_base;
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FGicSetPpiLevel(redis_base, int_id, trigger_way);
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}
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else
|
||
{
|
||
uintptr dis_base = instance_p->config.dis_base;
|
||
FGicSetSpiLevel(dis_base, int_id, trigger_way);
|
||
}
|
||
|
||
return FGIC_SUCCESS ;
|
||
}
|
||
|
||
/**
|
||
* @name: u32 FGicGetTriggerLevel(FGic *instance_p,s32 int_id)
|
||
* @msg: Gets the interrupt triggering mode based on the current interrupt number
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance
|
||
* @param {s32} int_id is interrupt id
|
||
* @return {u32} triggering mode
|
||
*/
|
||
u32 FGicGetTriggerLevel(FGic *instance_p, s32 int_id)
|
||
{
|
||
u32 trigger_way;
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
|
||
|
||
if (int_id > instance_p->max_spi_num)
|
||
{
|
||
FGIC_DEBUG_E("int_id is over max spi num for FGicGetTriggerLevel.");
|
||
return (u32)FGIC_CTLR_ERR_IN_GET;
|
||
}
|
||
|
||
if (int_id <= FGIC_SGI_END_ID)
|
||
{
|
||
uintptr redis_base = instance_p->redis_base;
|
||
trigger_way = FGicGetSgiLevel(redis_base, int_id);
|
||
}
|
||
else if (int_id <= FGIC_PPI_END_ID)
|
||
{
|
||
uintptr redis_base = instance_p->redis_base;
|
||
trigger_way = FGicGetPpiLevel(redis_base, int_id);
|
||
}
|
||
else
|
||
{
|
||
uintptr dis_base = instance_p->config.dis_base;
|
||
trigger_way = FGicGetSpiLevel(dis_base, int_id);
|
||
}
|
||
|
||
return trigger_way ;
|
||
}
|
||
|
||
/**
|
||
* @name: FGicSetSpiAffinityRouting
|
||
* @msg: Set intermediate routing information for a specific SPI interrupt
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @param {u32} int_id is interrupt vector for spi
|
||
* @param {SPI_ROUTING_MODE} route_mode is the interrupt routing mode.
|
||
* @param {u64} affinity is the affinity level ，format is
|
||
* |--------[bit39-32]-------[bit23-16]-------------[bit15-8]--------[bit7-0]
|
||
* |--------Affinity level3-----Affinity level2-----Affinity level1---Affinity level0
|
||
* @return {*}
|
||
*/
|
||
FError FGicSetSpiAffinityRouting(FGic *instance_p, s32 int_id, SPI_ROUTING_MODE route_mode, u64 affinity)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
uintptr dis_base = instance_p->config.dis_base;
|
||
|
||
if ((int_id > instance_p->max_spi_num) || (int_id <= FGIC_PPI_END_ID))
|
||
{
|
||
FGIC_DEBUG_E("int_id %d is out of range.", int_id);
|
||
return FGIC_CTLR_ERR_IN_SET;
|
||
}
|
||
|
||
FGicSetSpiRoute(dis_base, int_id, route_mode, affinity);
|
||
return FGIC_SUCCESS;
|
||
}
|
||
|
||
|
||
/**
|
||
* @name: FGicGetAffinityRouting
|
||
* @msg: Get intermediate routing information for a specific SPI interrupt
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @param {u32} int_id is interrupt vector for spi
|
||
* @param {SPI_ROUTING_MODE} *route_mode_p is a pointer to get interrupt routing mode.
|
||
* @param {u64} *affinity_p is pointer to get affinity level ,format is
|
||
* |--------[bit39-32]-------[bit23-16]-------------[bit15-8]--------[bit7-0]
|
||
* |--------Affinity level3-----Affinity level2-----Affinity level1---Affinity level0
|
||
* @return {FError}
|
||
*/
|
||
FError FGicGetAffinityRouting(FGic *instance_p, s32 int_id, SPI_ROUTING_MODE *route_mode_p, u64 *affinity_p)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
FASSERT(route_mode_p != NULL);
|
||
FASSERT(affinity_p != NULL);
|
||
uintptr dis_base = instance_p->config.dis_base;
|
||
u64 reg;
|
||
|
||
if ((int_id > instance_p->max_spi_num) || (int_id <= FGIC_PPI_END_ID))
|
||
{
|
||
FGIC_DEBUG_E("int_id %d is out of range.", int_id);
|
||
return (u32)FGIC_CTLR_ERR_IN_GET;
|
||
}
|
||
|
||
reg = FGicGetSpiRoute(dis_base, int_id);
|
||
*route_mode_p = reg & SPI_ROUTING_TO_ANY;
|
||
*affinity_p = reg & FGIC_GICD_IROUTER_AFFINITY_MASK;
|
||
return FGIC_SUCCESS;
|
||
}
|
||
|
||
|
||
/**
|
||
* @name: FGicGenerateSgi
|
||
* @msg: This interface is used for software generated interrupts
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @param {u32} int_id is interrupt vector for spi
|
||
* @param {u32} target_list is the set of PEs for which SGI interrupts will be generated. Each bit corresponds to the PE within a cluster with an Affinity 0 value equal to the bit number.
|
||
* @param {SGI_ROUTING_MODE} routing_mode is Interrupt Routing Mode.
|
||
* @param {u64} affinity is the affinity level ,format is
|
||
* |--------[bit55-48]-------[bit39-32]-------------[bit23-16]
|
||
* |--------Affinity level3-----Affinity level2-----Affinity level1
|
||
* @return {*}
|
||
*/
|
||
FError FGicGenerateSgi(FGic *instance_p, s32 int_id, u32 target_list, SGI_ROUTING_MODE routing_mode, u64 affinity)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
|
||
if (int_id > FGIC_SGI_END_ID)
|
||
{
|
||
FGIC_DEBUG_E("int_id %d is out of range.", int_id);
|
||
return FGIC_CTLR_ERR_IN_SET;
|
||
}
|
||
|
||
FGicSetICC_SGI1R((int_id & FGIC_ICC_SGI1R_INTID_MASK) << 24, target_list, routing_mode, affinity);
|
||
return FGIC_SUCCESS;
|
||
}
|
||
|
||
/**
|
||
* @name: FGicDeactionInterrupt
|
||
* @msg: Deactive Interruption of the current active state
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @param {s32} int_id is interrupt id
|
||
*/
|
||
void FGicDeactionInterrupt(FGic *instance_p, s32 int_id)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
FGicSetICC_EOIR1(int_id);
|
||
}
|
||
|
||
/**
|
||
* @name: FGicAcknowledgeInt
|
||
* @msg: Acknowledge pending interrupt
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @return {s32} interrupt id
|
||
*/
|
||
s32 FGicAcknowledgeInt(FGic *instance_p)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
return FGicGetICC_APR1();
|
||
}
|
||
|
||
|
||
/**
|
||
* @name: FGicSetPriorityFilter
|
||
* @msg: By setting the parameter of ICC_PMR, the interrupt range that the interrupt controller can respond to is determined
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @param {u32} priority_mask . If the priority of an interrupt is lower than the value indicated by this field, the interface signals the interrupt to the PE.
|
||
* The reference values of priority_mask are as follows
|
||
* |priority_mask---------------256-------254--------252------248-------240
|
||
* |Implemented priority bits---[7:0]----[7:1]------[7:2]-----[7:3]-----[7:4]
|
||
* |priority the growing steps--any-----even value----4---------8--------16
|
||
*/
|
||
void FGicSetPriorityFilter(FGic *instance_p, u32 priority_mask)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
|
||
FGicSetICC_PMR(priority_mask);
|
||
}
|
||
|
||
|
||
/**
|
||
* @name: FGicGetPriorityFilter
|
||
* @msg: Gets the current priority filtering value
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @return {u32} Priority Mask for the CPU interface . If the priority of an interrupt is lower than the value
|
||
* indicated by this field, the interface signals the interrupt to the PE.
|
||
* The reference values of priority_mask are as follows
|
||
* |return value----------------256-------254--------252------248-------240
|
||
* |Implemented priority bits---[7:0]----[7:1]------[7:2]-----[7:3]-----[7:4]
|
||
* |priority the growing steps--any-----even value----4---------8--------16
|
||
*/
|
||
u32 FGicGetPriorityFilter(FGic *instance_p)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
|
||
return FGicGetICC_PMR();
|
||
}
|
||
|
||
|
||
/**
|
||
* @name: FGicGetPriorityGroup
|
||
* @msg: Get Binary point value
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @return {u32} The relationship between Binary point value and grouping is as follows
|
||
* |return value----------------0-------1--------2------3-------4------5------6-------7
|
||
* |Group priority field------[---]----[7:1]---[7:2]--[7:3]---[7:4]---[7:5]---[7:6]---[7]
|
||
* |Subpriority field---------[---]-----[0]----[1:0]--[2:0]---[3:0]---[4:0]---[5:0]---[6:0]
|
||
*/
|
||
u32 FGicGetPriorityGroup(FGic *instance_p)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
|
||
return FGicGetICC_BPR1();
|
||
}
|
||
|
||
/**
|
||
* @name: FGicSetPriorityGroup
|
||
* @msg: Sets the value of the current group priority
|
||
* @param {FGic} *instance_p is a pointer to the FGic instance.
|
||
* @param {u32} binary_point : The value of this field controls how the 8-bit interrupt priority field is split into a group priority field
|
||
* The relationship between binary_point value and grouping is as follows
|
||
* |binary_point----------------0-------1--------2------3-------4------5------6-------7
|
||
* |Group priority field------[---]----[7:1]---[7:2]--[7:3]---[7:4]---[7:5]---[7:6]---[7]
|
||
* |Subpriority field---------[---]-----[0]----[1:0]--[2:0]---[3:0]---[4:0]---[5:0]---[6:0]
|
||
*/
|
||
void FGicSetPriorityGroup(FGic *instance_p, u32 binary_point)
|
||
{
|
||
FASSERT(instance_p);
|
||
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
||
|
||
FGicSetICC_BPR1(binary_point);
|
||
}
|
||
|
||
|