264 lines
12 KiB
C
264 lines
12 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-02-20 CDT first version
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#include "irq_config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 ch0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_RX_DMA_INSTANCE CM_DMA1
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#define SPI1_RX_DMA_CHANNEL DMA_CH0
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#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
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#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
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#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
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#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
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#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
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#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_RX_DMA_INSTANCE CM_DMA1
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#define SPI3_RX_DMA_CHANNEL DMA_CH0
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#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0
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#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
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#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
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#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
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#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
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#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
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#define I2C1_TX_DMA_INSTANCE CM_DMA1
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#define I2C1_TX_DMA_CHANNEL DMA_CH0
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#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
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#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
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#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
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#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
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#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
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#endif
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/* DMA1 ch1 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_TX_DMA_INSTANCE CM_DMA1
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#define SPI1_TX_DMA_CHANNEL DMA_CH1
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#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
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#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
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#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
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#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
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#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
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#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_TX_DMA_INSTANCE CM_DMA1
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#define SPI3_TX_DMA_CHANNEL DMA_CH1
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#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1
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#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
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#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
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#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
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#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
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#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
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#define I2C1_RX_DMA_INSTANCE CM_DMA1
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#define I2C1_RX_DMA_CHANNEL DMA_CH1
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#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
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#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
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#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
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#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
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#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
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#endif
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/* DMA1 ch2 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_RX_DMA_INSTANCE CM_DMA1
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#define SPI2_RX_DMA_CHANNEL DMA_CH2
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#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
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#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
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#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
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#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
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#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
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#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
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#define I2C2_TX_DMA_INSTANCE CM_DMA1
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#define I2C2_TX_DMA_CHANNEL DMA_CH2
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#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
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#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
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#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
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#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
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#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
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#endif
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/* DMA1 ch3 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_TX_DMA_INSTANCE CM_DMA1
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#define SPI2_TX_DMA_CHANNEL DMA_CH3
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#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
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#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
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#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
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#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
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#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
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#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
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#define I2C2_RX_DMA_INSTANCE CM_DMA1
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#define I2C2_RX_DMA_CHANNEL DMA_CH3
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#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
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#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
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#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
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#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
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#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
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#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
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#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
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#define ADC1_EOCA_DMA_CHANNEL DMA_CH3
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#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3
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#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
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#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
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#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
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#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3
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#endif
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/* DMA1 ch4 */
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#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
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#define UART5_RX_DMA_INSTANCE CM_DMA1
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#define UART5_RX_DMA_CHANNEL DMA_CH4
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#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4
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#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
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#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
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#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
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#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
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#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
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#define ADC2_EOCA_DMA_INSTANCE CM_DMA1
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#define ADC2_EOCA_DMA_CHANNEL DMA_CH4
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#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4
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#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
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#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
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#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
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#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4
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#endif
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/* DMA1 ch5 */
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#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
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#define UART5_TX_DMA_INSTANCE CM_DMA1
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#define UART5_TX_DMA_CHANNEL DMA_CH5
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#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5
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#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
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#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
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#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
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#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
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#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
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#define ADC3_EOCA_DMA_INSTANCE CM_DMA1
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#define ADC3_EOCA_DMA_CHANNEL DMA_CH5
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#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5
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#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
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#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
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#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
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#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5
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#endif
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/* DMA2 ch0 */
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#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_RX_DMA_INSTANCE CM_DMA2
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#define UART1_RX_DMA_CHANNEL DMA_CH0
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#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
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#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
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#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
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#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
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#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
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#endif
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/* DMA2 ch1 */
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#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART1_TX_DMA_INSTANCE CM_DMA2
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#define UART1_TX_DMA_CHANNEL DMA_CH1
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#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
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#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
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#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
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#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
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#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
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#endif
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/* DMA2 ch2 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_RX_DMA_INSTANCE CM_DMA2
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#define UART2_RX_DMA_CHANNEL DMA_CH2
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#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
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#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
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#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
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#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
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#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
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#endif
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/* DMA2 ch3 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_TX_DMA_INSTANCE CM_DMA2
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#define UART2_TX_DMA_CHANNEL DMA_CH3
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#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
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#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
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#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
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#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
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#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
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#endif
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/* DMA2 ch4 */
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#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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#define UART4_RX_DMA_INSTANCE CM_DMA2
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#define UART4_RX_DMA_CHANNEL DMA_CH4
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#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4
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#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
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#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
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#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
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#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
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#endif
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/* DMA2 ch5 */
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#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
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#define UART4_TX_DMA_INSTANCE CM_DMA2
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#define UART4_TX_DMA_CHANNEL DMA_CH5
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#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5
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#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
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#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
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#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
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#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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