546 lines
13 KiB
C
546 lines
13 KiB
C
#include "LPC177x_8x.h"
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#include "lpc177x_8x_pinsel.h"
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#include "emac.h"
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#include <rtthread.h>
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#include "lwipopts.h"
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#include <netif/ethernetif.h>
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#define EMAC_PHY_AUTO 0
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#define EMAC_PHY_10MBIT 1
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#define EMAC_PHY_100MBIT 2
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#define MAX_ADDR_LEN 6
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struct lpc17xx_emac
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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rt_uint8_t phy_mode;
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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};
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static struct lpc17xx_emac lpc17xx_emac_device;
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static struct rt_semaphore sem_lock;
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static struct rt_event tx_event;
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/* Local Function Prototypes */
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static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value);
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static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
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void ENET_IRQHandler(void)
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{
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rt_uint32_t status;
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/* enter interrupt */
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rt_interrupt_enter();
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status = LPC_EMAC->IntStatus;
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if (status & INT_RX_DONE)
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{
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/* Disable EMAC RxDone interrupts. */
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LPC_EMAC->IntEnable = INT_TX_DONE;
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/* a frame has been received */
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eth_device_ready(&(lpc17xx_emac_device.parent));
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}
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else if (status & INT_TX_DONE)
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{
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/* set event */
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rt_event_send(&tx_event, 0x01);
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}
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if (status & INT_RX_OVERRUN)
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{
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rt_kprintf("rx overrun\n");
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}
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if (status & INT_TX_UNDERRUN)
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{
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rt_kprintf("tx underrun\n");
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}
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/* Clear the interrupt. */
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LPC_EMAC->IntClear = status;
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/* phy write */
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static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
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{
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unsigned int tout;
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LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
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LPC_EMAC->MWTD = Value;
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/* Wait utill operation completed */
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tout = 0;
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for (tout = 0; tout < MII_WR_TOUT; tout++)
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{
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if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
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{
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break;
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}
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}
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}
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/* phy read */
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static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
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{
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rt_uint32_t tout;
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LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
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LPC_EMAC->MCMD = MCMD_READ;
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/* Wait until operation completed */
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tout = 0;
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for (tout = 0; tout < MII_RD_TOUT; tout++)
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{
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if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
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{
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break;
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}
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}
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LPC_EMAC->MCMD = 0;
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return (LPC_EMAC->MRDD);
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}
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/* init rx descriptor */
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rt_inline void rx_descr_init (void)
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{
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rt_uint32_t i;
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for (i = 0; i < NUM_RX_FRAG; i++)
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{
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RX_DESC_PACKET(i) = RX_BUF(i);
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RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
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RX_STAT_INFO(i) = 0;
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RX_STAT_HASHCRC(i) = 0;
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}
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/* Set EMAC Receive Descriptor Registers. */
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LPC_EMAC->RxDescriptor = RX_DESC_BASE;
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LPC_EMAC->RxStatus = RX_STAT_BASE;
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LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
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/* Rx Descriptors Point to 0 */
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LPC_EMAC->RxConsumeIndex = 0;
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}
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/* init tx descriptor */
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rt_inline void tx_descr_init (void)
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{
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rt_uint32_t i;
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for (i = 0; i < NUM_TX_FRAG; i++)
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{
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TX_DESC_PACKET(i) = TX_BUF(i);
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TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
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TX_STAT_INFO(i) = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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LPC_EMAC->TxDescriptor = TX_DESC_BASE;
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LPC_EMAC->TxStatus = TX_STAT_BASE;
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LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
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/* Tx Descriptors Point to 0 */
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LPC_EMAC->TxProduceIndex = 0;
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}
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/*
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TX_EN P1_4
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TXD0 P1_0
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TXD1 P1_1
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RXD0 P1_9
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RXD1 P1_10
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RX_ER P1_14
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CRS_DV P1_8
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MDC P1_16
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MDIO P1_17
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PHY_RESET P3_19
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REF_CLK P1_15
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*/
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static rt_err_t lpc17xx_emac_init(rt_device_t dev)
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{
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/* Initialize the EMAC ethernet controller. */
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rt_uint32_t regv, tout, id1, id2;
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/* Power Up the EMAC controller. */
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LPC_SC->PCONP |= (1UL<<30);
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/* config RESET */
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PINSEL_ConfigPin(3, 19, 0);
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PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
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LPC_GPIO3->DIR |= 1<<19;
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LPC_GPIO3->CLR = 1<<19;
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/* Enable P1 Ethernet Pins. */
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PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */
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PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */
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PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */
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PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */
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PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */
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PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
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PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
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PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
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PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
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PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
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LPC_GPIO3->SET = 1<<19;
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/* Reset all EMAC internal modules. */
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LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
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MAC1_SIM_RES | MAC1_SOFT_RES;
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LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
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/* A short delay after reset. */
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for (tout = 100; tout; tout--);
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/* Initialize MAC control registers. */
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LPC_EMAC->MAC1 = MAC1_PASS_ALL;
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LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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LPC_EMAC->MAXF = ETH_MAX_FLEN;
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LPC_EMAC->CLRT = CLRT_DEF;
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LPC_EMAC->IPGR = IPGR_DEF;
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/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
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/* Enable Reduced MII interface. */
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LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
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for (tout = 100; tout; tout--);
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LPC_EMAC->MCFG = MCFG_CLK_DIV20;
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/* Enable Reduced MII interface. */
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LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
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/* Reset Reduced MII Logic. */
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LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
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for (tout = 100; tout; tout--);
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LPC_EMAC->SUPP = SUPP_SPEED;
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/* Put the PHY in reset mode */
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write_PHY (PHY_REG_BMCR, 0x8000);
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for (tout = 1000; tout; tout--);
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// /* Wait for hardware reset to end. */
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// for (tout = 0; tout < 0x100000; tout++)
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// {
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// regv = read_PHY (PHY_REG_BMCR);
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// if (!(regv & 0x8000))
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// {
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// /* Reset complete */
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// break;
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// }
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// }
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// if (tout >= 0x100000)
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// {
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// rt_kprintf("reset failed\r\n");
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// return -RT_ERROR; /* reset failed */
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// }
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// /* Check if this is a DP83848C PHY. */
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// id1 = read_PHY (PHY_REG_IDR1);
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// id2 = read_PHY (PHY_REG_IDR2);
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//
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// if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
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// return -RT_ERROR;
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/* Configure the PHY device */
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/* Configure the PHY device */
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switch (lpc17xx_emac_device.phy_mode)
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{
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case EMAC_PHY_AUTO:
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/* Use autonegotiation about the link speed. */
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write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
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/* Wait to complete Auto_Negotiation. */
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// for (tout = 0; tout < 0x100000; tout++)
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// {
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// regv = read_PHY (PHY_REG_BMSR);
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// if (regv & 0x0020)
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// {
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// /* Autonegotiation Complete. */
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// break;
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// }
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// }
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break;
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case EMAC_PHY_10MBIT:
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/* Connect at 10MBit */
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write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
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break;
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case EMAC_PHY_100MBIT:
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/* Connect at 100MBit */
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write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
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break;
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}
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if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
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// /* Check the link status. */
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// for (tout = 0; tout < 0x10000; tout++)
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// {
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// regv = read_PHY (PHY_REG_STS);
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// if (regv & 0x0001)
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// {
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// /* Link is on. */
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// break;
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// }
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// }
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// if (tout >= 0x10000) return -RT_ERROR;
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regv = 0x0004;
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/* Configure Full/Half Duplex mode. */
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if (regv & 0x0004)
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{
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/* Full duplex is enabled. */
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LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
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LPC_EMAC->Command |= CR_FULL_DUP;
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LPC_EMAC->IPGT = IPGT_FULL_DUP;
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}
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else
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{
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/* Half duplex mode. */
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LPC_EMAC->IPGT = IPGT_HALF_DUP;
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}
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/* Configure 100MBit/10MBit mode. */
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if (regv & 0x0002)
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{
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/* 10MBit mode. */
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LPC_EMAC->SUPP = 0;
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}
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else
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{
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/* 100MBit mode. */
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LPC_EMAC->SUPP = SUPP_SPEED;
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}
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/* Set the Ethernet MAC Address registers */
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LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
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LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
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LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
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/* Initialize Tx and Rx DMA Descriptors */
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rx_descr_init ();
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tx_descr_init ();
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/* Receive Broadcast and Perfect Match Packets */
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LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
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/* Reset all interrupts */
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LPC_EMAC->IntClear = 0xFFFF;
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/* Enable EMAC interrupts. */
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LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
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/* Enable receive and transmit mode of MAC Ethernet core */
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LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
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LPC_EMAC->MAC1 |= MAC1_REC_EN;
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/* Enable the ENET Interrupt */
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NVIC_EnableIRQ(ENET_IRQn);
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return RT_EOK;
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}
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static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
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{
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return RT_EOK;
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}
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static rt_err_t lpc17xx_emac_close(rt_device_t dev)
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{
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return RT_EOK;
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}
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static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t lpc17xx_emac_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* EtherNet Device Interface */
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/* transmit packet. */
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rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
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{
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rt_uint32_t Index, IndexNext;
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struct pbuf *q;
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rt_uint8_t *ptr;
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/* calculate next index */
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IndexNext = LPC_EMAC->TxProduceIndex + 1;
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if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
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/* check whether block is full */
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while (IndexNext == LPC_EMAC->TxConsumeIndex)
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{
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rt_err_t result;
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rt_uint32_t recved;
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/* there is no block yet, wait a flag */
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result = rt_event_recv(&tx_event, 0x01,
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RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
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RT_ASSERT(result == RT_EOK);
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}
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/* lock EMAC device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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/* get produce index */
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Index = LPC_EMAC->TxProduceIndex;
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/* calculate next index */
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IndexNext = LPC_EMAC->TxProduceIndex + 1;
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if(IndexNext > LPC_EMAC->TxDescriptorNumber)
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IndexNext = 0;
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/* copy data to tx buffer */
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q = p;
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ptr = (rt_uint8_t*)TX_BUF(Index);
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while (q)
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{
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memcpy(ptr, q->payload, q->len);
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ptr += q->len;
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q = q->next;
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}
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TX_DESC_CTRL(Index) &= ~0x7ff;
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TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
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/* change index to the next */
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LPC_EMAC->TxProduceIndex = IndexNext;
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/* unlock EMAC device */
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rt_sem_release(&sem_lock);
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return RT_EOK;
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}
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/* reception packet. */
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struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
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{
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struct pbuf* p;
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rt_uint32_t size;
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rt_uint32_t Index;
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/* init p pointer */
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p = RT_NULL;
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/* lock EMAC device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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Index = LPC_EMAC->RxConsumeIndex;
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if(Index != LPC_EMAC->RxProduceIndex)
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{
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size = (RX_STAT_INFO(Index) & 0x7ff)+1;
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if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
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/* allocate buffer */
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p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
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if (p != RT_NULL)
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{
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struct pbuf* q;
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rt_uint8_t *ptr;
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ptr = (rt_uint8_t*)RX_BUF(Index);
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for (q = p; q != RT_NULL; q= q->next)
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{
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memcpy(q->payload, ptr, q->len);
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ptr += q->len;
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}
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}
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/* move Index to the next */
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if(++Index > LPC_EMAC->RxDescriptorNumber)
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Index = 0;
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/* set consume index */
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LPC_EMAC->RxConsumeIndex = Index;
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}
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else
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{
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/* Enable RxDone interrupt */
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LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
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}
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/* unlock EMAC device */
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rt_sem_release(&sem_lock);
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return p;
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}
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void lpc17xx_emac_hw_init(void)
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{
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rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
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rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
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/* set autonegotiation mode */
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lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
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// OUI 00-60-37 NXP Semiconductors
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lpc17xx_emac_device.dev_addr[0] = 0x00;
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lpc17xx_emac_device.dev_addr[1] = 0x60;
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lpc17xx_emac_device.dev_addr[2] = 0x37;
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/* set mac address: (only for test) */
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lpc17xx_emac_device.dev_addr[3] = 0x12;
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lpc17xx_emac_device.dev_addr[4] = 0x34;
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lpc17xx_emac_device.dev_addr[5] = 0x56;
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lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
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lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
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lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close;
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lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read;
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lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write;
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lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control;
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lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
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lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx;
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lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx;
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eth_device_init(&(lpc17xx_emac_device.parent), "e0");
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}
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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void emac_dump()
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{
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rt_kprintf("Command : %08x\n", LPC_EMAC->Command);
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rt_kprintf("Status : %08x\n", LPC_EMAC->Status);
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rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
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rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
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rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
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rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
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}
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FINSH_FUNCTION_EXPORT(emac_dump, dump emac register);
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#endif
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