1639 lines
96 KiB
C
1639 lines
96 KiB
C
/**************************************************************************//**
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* @file core_cm3.h
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
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* @version V3.30
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* @date 17. February 2014
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2009 - 2014 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __CORE_CM3_H_GENERIC
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#define __CORE_CM3_H_GENERIC
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/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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CMSIS violates the following MISRA-C:2004 rules:
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\li Required Rule 8.5, object/function definition in header file.<br>
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Function definitions in header files are used to allow 'inlining'.
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\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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Unions are used for effective representation of core registers.
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\li Advisory Rule 19.7, Function-like macro defined.<br>
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Function-like macros are used to allow more efficient code.
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*/
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/*******************************************************************************
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* CMSIS definitions
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******************************************************************************/
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/** \ingroup Cortex_M3
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@{
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*/
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/* CMSIS CM3 definitions */
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#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
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#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
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#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
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__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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#define __CORTEX_M (0x03) /*!< Cortex-M Core */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#define __STATIC_INLINE static __inline
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#define __STATIC_INLINE static inline
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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#define __STATIC_INLINE static inline
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#elif defined ( __TMS470__ )
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#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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#define __STATIC_INLINE static inline
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#define __STATIC_INLINE static inline
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#elif defined ( __CSMC__ ) /* Cosmic */
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#define __packed
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#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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#define __STATIC_INLINE static inline
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#endif
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/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
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*/
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#define __FPU_USED 0
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#if defined ( __CC_ARM )
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#if defined __TARGET_FPU_VFP
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __GNUC__ )
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __ICCARM__ )
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#if defined __ARMVFP__
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __TMS470__ )
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#if defined __TI__VFP_SUPPORT____
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __TASKING__ )
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#if defined __FPU_VFP__
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __CSMC__ ) /* Cosmic */
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#if ( __CSMC__ & 0x400) // FPU present for parser
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#endif
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#include <stdint.h> /* standard types definitions */
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#include <core_cmInstr.h> /* Core Instruction Access */
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#include <core_cmFunc.h> /* Core Function Access */
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#endif /* __CORE_CM3_H_GENERIC */
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#ifndef __CMSIS_GENERIC
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#ifndef __CORE_CM3_H_DEPENDANT
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#define __CORE_CM3_H_DEPENDANT
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/* check device defines and use defaults */
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#if defined __CHECK_DEVICE_DEFINES
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#ifndef __CM3_REV
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#define __CM3_REV 0x0200
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#warning "__CM3_REV not defined in device header file; using default!"
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#endif
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#ifndef __MPU_PRESENT
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#define __MPU_PRESENT 0
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#warning "__MPU_PRESENT not defined in device header file; using default!"
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#endif
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#ifndef __NVIC_PRIO_BITS
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#define __NVIC_PRIO_BITS 4
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#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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#endif
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#ifndef __Vendor_SysTickConfig
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#define __Vendor_SysTickConfig 0
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#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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#endif
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#endif
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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\defgroup CMSIS_glob_defs CMSIS Global Defines
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<strong>IO Type Qualifiers</strong> are used
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\li to specify the access to peripheral variables.
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\li for automatic generation of peripheral register debug information.
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/*@} end of group Cortex_M3 */
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/*******************************************************************************
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* Register Abstraction
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Core Register contain:
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- Core Register
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- Core NVIC Register
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- Core SCB Register
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- Core SysTick Register
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- Core Debug Register
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- Core MPU Register
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******************************************************************************/
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/** \defgroup CMSIS_core_register Defines and Type Definitions
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\brief Type definitions and defines for Cortex-M processor based devices.
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*/
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/** \ingroup CMSIS_core_register
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\defgroup CMSIS_CORE Status and Control Registers
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\brief Core Register type definitions.
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@{
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*/
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/** \brief Union type to access the Application Program Status Register (APSR).
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*/
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typedef union
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{
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struct
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{
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#if (__CORTEX_M != 0x04)
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uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
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#else
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uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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#endif
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uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} APSR_Type;
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/** \brief Union type to access the Interrupt Program Status Register (IPSR).
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*/
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typedef union
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{
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struct
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{
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uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} IPSR_Type;
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/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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*/
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typedef union
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{
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struct
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{
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uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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#if (__CORTEX_M != 0x04)
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uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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#else
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uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
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#endif
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uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} xPSR_Type;
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/** \brief Union type to access the Control Registers (CONTROL).
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*/
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typedef union
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{
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struct
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{
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uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} CONTROL_Type;
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/*@} end of group CMSIS_CORE */
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/** \ingroup CMSIS_core_register
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\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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\brief Type definitions for the NVIC Registers
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@{
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*/
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/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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*/
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typedef struct
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{
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__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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uint32_t RESERVED0[24];
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__IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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uint32_t RSERVED1[24];
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__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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uint32_t RESERVED2[24];
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__IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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uint32_t RESERVED3[24];
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__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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uint32_t RESERVED4[56];
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__IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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uint32_t RESERVED5[644];
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__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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} NVIC_Type;
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/* Software Triggered Interrupt Register Definitions */
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#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
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#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
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/*@} end of group CMSIS_NVIC */
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/** \ingroup CMSIS_core_register
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\defgroup CMSIS_SCB System Control Block (SCB)
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\brief Type definitions for the System Control Block Registers
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@{
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*/
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/** \brief Structure type to access the System Control Block (SCB).
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*/
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typedef struct
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{
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__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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__IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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__IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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__IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
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__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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__IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
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__IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
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__IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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uint32_t RESERVED0[5];
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__IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
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} SCB_Type;
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/* SCB CPUID Register Definitions */
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#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
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#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
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#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
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#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
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#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
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/* SCB Interrupt Control State Register Definitions */
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#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
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#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
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#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
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#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
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#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
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#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
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#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
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#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
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#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
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#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
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#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
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#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
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#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
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/* SCB Vector Table Offset Register Definitions */
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#if (__CM3_REV < 0x0201) /* core r2p1 */
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#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
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#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
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#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
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#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
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#else
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#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
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#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
|
#endif
|
|
|
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
|
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
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|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
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|
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|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
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|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
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|
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|
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
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|
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|
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
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|
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
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|
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|
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
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|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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|
|
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
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|
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|
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
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|
#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
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|
|
|
/* SCB System Control Register Definitions */
|
|
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
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|
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|
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
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#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
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|
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|
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
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|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
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|
|
|
/* SCB Configuration Control Register Definitions */
|
|
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
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|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
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|
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|
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
|
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#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
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|
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#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
|
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#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
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|
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|
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
|
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|
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
|
|
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
|
|
|
|
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
|
|
#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
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|
|
|
/* SCB System Handler Control and State Register Definitions */
|
|
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
|
|
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
|
|
|
|
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
|
|
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
|
|
|
|
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
|
|
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
|
|
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|
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
|
|
|
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
|
|
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
|
|
|
|
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
|
|
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
|
|
|
|
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
|
|
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
|
|
|
|
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
|
|
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
|
|
|
|
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
|
|
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
|
|
|
|
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
|
|
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
|
|
|
|
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
|
|
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
|
|
|
|
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
|
|
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
|
|
|
|
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
|
|
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
|
|
|
|
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
|
|
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
|
|
|
|
/* SCB Configurable Fault Status Registers Definitions */
|
|
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
|
|
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
|
|
|
|
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
|
|
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
|
|
|
|
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
|
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
|
|
|
/* SCB Hard Fault Status Registers Definitions */
|
|
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
|
|
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
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|
|
|
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
|
|
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
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|
|
|
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
|
|
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
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|
|
|
/* SCB Debug Fault Status Register Definitions */
|
|
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
|
|
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
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|
|
|
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
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#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
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|
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|
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
|
|
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
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|
|
|
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
|
|
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
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|
|
|
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
|
|
#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
|
|
|
|
/*@} end of group CMSIS_SCB */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
|
\brief Type definitions for the System Control and ID Register not in the SCB
|
|
@{
|
|
*/
|
|
|
|
/** \brief Structure type to access the System Control and ID Register not in the SCB.
|
|
*/
|
|
typedef struct
|
|
{
|
|
uint32_t RESERVED0[1];
|
|
__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
|
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
|
|
__IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
|
#else
|
|
uint32_t RESERVED1[1];
|
|
#endif
|
|
} SCnSCB_Type;
|
|
|
|
/* Interrupt Controller Type Register Definitions */
|
|
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
|
|
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
|
|
|
|
/* Auxiliary Control Register Definitions */
|
|
|
|
#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
|
|
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
|
|
|
|
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
|
|
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
|
|
|
|
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
|
|
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
|
|
|
|
/*@} end of group CMSIS_SCnotSCB */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
|
\brief Type definitions for the System Timer Registers.
|
|
@{
|
|
*/
|
|
|
|
/** \brief Structure type to access the System Timer (SysTick).
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
|
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
|
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
|
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
|
} SysTick_Type;
|
|
|
|
/* SysTick Control / Status Register Definitions */
|
|
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
|
|
|
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
|
|
|
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
|
|
|
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
|
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
|
|
|
/* SysTick Reload Register Definitions */
|
|
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
|
|
|
/* SysTick Current Register Definitions */
|
|
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
|
|
|
/* SysTick Calibration Register Definitions */
|
|
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
|
|
|
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
|
|
|
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
|
|
|
/*@} end of group CMSIS_SysTick */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
|
|
\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
|
|
@{
|
|
*/
|
|
|
|
/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
|
|
*/
|
|
typedef struct
|
|
{
|
|
__O union
|
|
{
|
|
__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
|
|
__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
|
|
__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
|
|
} PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
|
|
uint32_t RESERVED0[864];
|
|
__IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
|
|
uint32_t RESERVED1[15];
|
|
__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
|
|
uint32_t RESERVED2[15];
|
|
__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
|
|
uint32_t RESERVED3[29];
|
|
__O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
|
|
__I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
|
|
__IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
|
|
uint32_t RESERVED4[43];
|
|
__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
|
|
__I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
|
|
uint32_t RESERVED5[6];
|
|
__I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
|
|
__I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
|
|
__I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
|
|
__I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
|
|
__I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
|
|
__I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
|
|
__I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
|
|
__I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
|
|
__I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
|
|
__I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
|
|
__I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
|
|
__I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
|
|
} ITM_Type;
|
|
|
|
/* ITM Trace Privilege Register Definitions */
|
|
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
|
|
#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
|
|
|
|
/* ITM Trace Control Register Definitions */
|
|
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
|
|
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
|
|
|
|
#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
|
|
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
|
|
|
|
#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
|
|
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
|
|
|
|
#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
|
|
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
|
|
|
|
#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
|
|
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
|
|
|
|
#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
|
|
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
|
|
|
|
#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
|
|
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
|
|
|
|
#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
|
|
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
|
|
|
|
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
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#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
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|
|
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/* ITM Integration Write Register Definitions */
|
|
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
|
|
#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
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|
|
|
/* ITM Integration Read Register Definitions */
|
|
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
|
|
#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
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|
|
|
/* ITM Integration Mode Control Register Definitions */
|
|
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
|
|
#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
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|
|
|
/* ITM Lock Status Register Definitions */
|
|
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
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|
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
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|
|
|
#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
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|
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
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|
|
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#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
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|
#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
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|
|
|
/*@}*/ /* end of group CMSIS_ITM */
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|
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/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
|
|
\brief Type definitions for the Data Watchpoint and Trace (DWT)
|
|
@{
|
|
*/
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|
|
|
/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
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|
__IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
|
|
__IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
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|
__IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
|
|
__IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
|
|
__IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
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|
__IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
|
|
__I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
|
|
__IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
|
|
__IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
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|
__IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
|
|
uint32_t RESERVED0[1];
|
|
__IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
|
|
__IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
|
|
__IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
|
|
uint32_t RESERVED1[1];
|
|
__IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
|
|
__IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
|
|
__IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
|
|
uint32_t RESERVED2[1];
|
|
__IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
|
|
__IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
|
|
__IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
|
|
} DWT_Type;
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|
|
|
/* DWT Control Register Definitions */
|
|
#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
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|
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
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|
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|
#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
|
|
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
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|
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|
#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
|
|
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
|
|
|
|
#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
|
|
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
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|
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|
#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
|
|
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
|
|
|
|
#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
|
|
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
|
|
|
|
#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
|
|
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
|
|
|
|
#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
|
|
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
|
|
|
|
#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
|
|
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
|
|
|
|
#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
|
|
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
|
|
|
|
#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
|
|
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
|
|
|
|
#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
|
|
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
|
|
|
|
#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
|
|
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
|
|
|
|
#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
|
|
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
|
|
|
|
#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
|
|
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
|
|
|
|
#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
|
|
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
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|
|
|
#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
|
|
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
|
|
|
|
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
|
|
#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
|
|
|
|
/* DWT CPI Count Register Definitions */
|
|
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
|
|
#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
|
|
|
|
/* DWT Exception Overhead Count Register Definitions */
|
|
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
|
|
#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
|
|
|
|
/* DWT Sleep Count Register Definitions */
|
|
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
|
|
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
|
|
|
|
/* DWT LSU Count Register Definitions */
|
|
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
|
|
#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
|
|
|
|
/* DWT Folded-instruction Count Register Definitions */
|
|
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
|
|
#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
|
|
|
|
/* DWT Comparator Mask Register Definitions */
|
|
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
|
|
#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
|
|
|
|
/* DWT Comparator Function Register Definitions */
|
|
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
|
|
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
|
|
|
|
#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
|
|
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
|
|
|
|
#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
|
|
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
|
|
|
|
#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
|
|
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
|
|
|
|
#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
|
|
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
|
|
|
|
#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
|
|
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
|
|
|
|
#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
|
|
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
|
|
|
|
#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
|
|
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
|
|
|
|
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
|
|
#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
|
|
|
|
/*@}*/ /* end of group CMSIS_DWT */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_TPI Trace Port Interface (TPI)
|
|
\brief Type definitions for the Trace Port Interface (TPI)
|
|
@{
|
|
*/
|
|
|
|
/** \brief Structure type to access the Trace Port Interface Register (TPI).
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
|
__IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
|
uint32_t RESERVED0[2];
|
|
__IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
|
uint32_t RESERVED1[55];
|
|
__IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
|
|
uint32_t RESERVED2[131];
|
|
__I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
|
|
__IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
|
__I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
|
uint32_t RESERVED3[759];
|
|
__I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
|
__I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
|
__I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
|
uint32_t RESERVED4[1];
|
|
__I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
|
|
__I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
|
|
__IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
|
|
uint32_t RESERVED5[39];
|
|
__IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
|
|
__IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
|
|
uint32_t RESERVED7[8];
|
|
__I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
|
|
__I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
|
|
} TPI_Type;
|
|
|
|
/* TPI Asynchronous Clock Prescaler Register Definitions */
|
|
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
|
|
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
|
|
|
|
/* TPI Selected Pin Protocol Register Definitions */
|
|
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
|
|
#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
|
|
|
|
/* TPI Formatter and Flush Status Register Definitions */
|
|
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
|
|
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
|
|
|
|
#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
|
|
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
|
|
|
|
#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
|
|
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
|
|
|
|
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
|
|
#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
|
|
|
|
/* TPI Formatter and Flush Control Register Definitions */
|
|
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
|
|
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
|
|
|
|
#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
|
|
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
|
|
|
|
/* TPI TRIGGER Register Definitions */
|
|
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
|
|
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
|
|
|
|
/* TPI Integration ETM Data Register Definitions (FIFO0) */
|
|
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
|
|
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
|
|
|
|
#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
|
|
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
|
|
|
|
#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
|
|
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
|
|
|
|
#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
|
|
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
|
|
|
|
#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
|
|
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
|
|
|
|
#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
|
|
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
|
|
|
|
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
|
|
#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
|
|
|
|
/* TPI ITATBCTR2 Register Definitions */
|
|
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
|
|
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
|
|
|
|
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
|
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
|
|
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
|
|
|
|
#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
|
|
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
|
|
|
|
#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
|
|
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
|
|
|
|
#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
|
|
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
|
|
|
|
#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
|
|
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
|
|
|
|
#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
|
|
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
|
|
|
|
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
|
|
#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
|
|
|
|
/* TPI ITATBCTR0 Register Definitions */
|
|
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
|
|
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
|
|
|
|
/* TPI Integration Mode Control Register Definitions */
|
|
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
|
|
#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
|
|
|
|
/* TPI DEVID Register Definitions */
|
|
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
|
|
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
|
|
|
|
#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
|
|
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
|
|
|
|
#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
|
|
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
|
|
|
|
#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
|
|
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
|
|
|
|
#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
|
|
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
|
|
|
|
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
|
|
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
|
|
|
|
/* TPI DEVTYPE Register Definitions */
|
|
#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
|
|
#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
|
|
|
|
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
|
|
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
|
|
|
/*@}*/ /* end of group CMSIS_TPI */
|
|
|
|
|
|
#if (__MPU_PRESENT == 1)
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
|
\brief Type definitions for the Memory Protection Unit (MPU)
|
|
@{
|
|
*/
|
|
|
|
/** \brief Structure type to access the Memory Protection Unit (MPU).
|
|
*/
|
|
typedef struct
|
|
{
|
|
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
|
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
|
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
|
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
|
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
|
__IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
|
|
__IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
|
|
__IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
|
|
__IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
|
|
__IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
|
|
__IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
|
} MPU_Type;
|
|
|
|
/* MPU Type Register */
|
|
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
|
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
|
|
|
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
|
|
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
|
|
|
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
|
|
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
|
|
|
|
/* MPU Control Register */
|
|
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
|
|
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
|
|
|
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
|
|
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
|
|
|
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
|
|
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
|
|
|
|
/* MPU Region Number Register */
|
|
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
|
|
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
|
|
|
|
/* MPU Region Base Address Register */
|
|
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
|
|
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
|
|
|
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
|
|
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
|
|
|
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
|
|
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
|
|
|
|
/* MPU Region Attribute and Size Register */
|
|
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
|
|
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
|
|
|
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
|
|
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
|
|
|
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
|
|
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
|
|
|
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
|
|
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
|
|
|
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
|
|
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
|
|
|
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
|
|
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
|
|
|
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
|
|
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
|
|
|
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
|
|
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
|
|
|
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
|
|
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
|
|
|
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
|
|
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
|
|
|
|
/*@} end of group CMSIS_MPU */
|
|
#endif
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
|
\brief Type definitions for the Core Debug Registers
|
|
@{
|
|
*/
|
|
|
|
/** \brief Structure type to access the Core Debug Register (CoreDebug).
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
|
|
__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
|
|
__IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
|
|
__IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
|
|
} CoreDebug_Type;
|
|
|
|
/* Debug Halting Control and Status Register */
|
|
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
|
|
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
|
|
|
|
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
|
|
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
|
|
|
|
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
|
|
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
|
|
|
|
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
|
|
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
|
|
|
|
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
|
|
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
|
|
|
|
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
|
|
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
|
|
|
|
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
|
|
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
|
|
|
|
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
|
|
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
|
|
|
|
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
|
|
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
|
|
|
|
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
|
|
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
|
|
|
|
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
|
|
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
|
|
|
|
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
|
|
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
|
|
|
|
/* Debug Core Register Selector Register */
|
|
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
|
|
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
|
|
|
|
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
|
|
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
|
|
|
|
/* Debug Exception and Monitor Control Register */
|
|
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
|
|
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
|
|
|
|
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
|
|
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
|
|
|
|
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
|
|
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
|
|
|
|
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
|
|
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
|
|
|
|
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
|
|
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
|
|
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
|
|
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
|
|
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
|
|
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
|
|
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
|
|
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
|
|
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
|
|
|
|
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
|
|
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
|
|
|
|
/*@} end of group CMSIS_CoreDebug */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_core_base Core Definitions
|
|
\brief Definitions for base addresses, unions, and structures.
|
|
@{
|
|
*/
|
|
|
|
/* Memory mapping of Cortex-M3 Hardware */
|
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
|
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
|
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
|
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
|
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
|
|
|
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
|
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
|
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
|
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
|
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
|
|
|
#if (__MPU_PRESENT == 1)
|
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
|
#endif
|
|
|
|
/*@} */
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
* Hardware Abstraction Layer
|
|
Core Function Interface contains:
|
|
- Core NVIC Functions
|
|
- Core SysTick Functions
|
|
- Core Debug Functions
|
|
- Core Register Access Functions
|
|
******************************************************************************/
|
|
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
|
*/
|
|
|
|
|
|
|
|
/* ########################## NVIC functions #################################### */
|
|
/** \ingroup CMSIS_Core_FunctionInterface
|
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
|
@{
|
|
*/
|
|
|
|
/** \brief Set Priority Grouping
|
|
|
|
The function sets the priority grouping field using the required unlock sequence.
|
|
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
|
|
Only values from 0..7 are used.
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
|
|
SCB->AIRCR = reg_value;
|
|
}
|
|
|
|
|
|
/** \brief Get Priority Grouping
|
|
|
|
The function reads the priority grouping field from the NVIC Interrupt Controller.
|
|
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
|
{
|
|
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
|
|
}
|
|
|
|
|
|
/** \brief Enable External Interrupt
|
|
|
|
The function enables a device-specific interrupt in the NVIC interrupt controller.
|
|
|
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
|
|
}
|
|
|
|
|
|
/** \brief Disable External Interrupt
|
|
|
|
The function disables a device-specific interrupt in the NVIC interrupt controller.
|
|
|
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
|
|
}
|
|
|
|
|
|
/** \brief Get Pending Interrupt
|
|
|
|
The function reads the pending register in the NVIC and returns the pending bit
|
|
for the specified interrupt.
|
|
|
|
\param [in] IRQn Interrupt number.
|
|
|
|
\return 0 Interrupt status is not pending.
|
|
\return 1 Interrupt status is pending.
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
|
|
}
|
|
|
|
|
|
/** \brief Set Pending Interrupt
|
|
|
|
The function sets the pending bit of an external interrupt.
|
|
|
|
\param [in] IRQn Interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
|
|
}
|
|
|
|
|
|
/** \brief Clear Pending Interrupt
|
|
|
|
The function clears the pending bit of an external interrupt.
|
|
|
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
|
|
}
|
|
|
|
|
|
/** \brief Get Active Interrupt
|
|
|
|
The function reads the active register in NVIC and returns the active bit.
|
|
|
|
\param [in] IRQn Interrupt number.
|
|
|
|
\return 0 Interrupt status is not active.
|
|
\return 1 Interrupt status is active.
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
|
{
|
|
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
|
|
}
|
|
|
|
|
|
/** \brief Set Interrupt Priority
|
|
|
|
The function sets the priority of an interrupt.
|
|
|
|
\note The priority cannot be set for every core interrupt.
|
|
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
*/
|
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
if(IRQn < 0) {
|
|
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
|
|
else {
|
|
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
|
|
}
|
|
|
|
|
|
/** \brief Get Interrupt Priority
|
|
|
|
The function reads the priority of an interrupt. The interrupt
|
|
number can be positive to specify an external (device specific)
|
|
interrupt, or negative to specify an internal (core) interrupt.
|
|
|
|
|
|
\param [in] IRQn Interrupt number.
|
|
\return Interrupt Priority. Value is aligned automatically to the implemented
|
|
priority bits of the microcontroller.
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
|
{
|
|
|
|
if(IRQn < 0) {
|
|
return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
|
|
else {
|
|
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
|
}
|
|
|
|
|
|
/** \brief Encode Priority
|
|
|
|
The function encodes the priority for an interrupt with the given priority group,
|
|
preemptive priority value, and subpriority value.
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
|
|
|
|
\param [in] PriorityGroup Used priority group.
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
|
|
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
|
|
|
|
return (
|
|
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
|
|
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
|
|
);
|
|
}
|
|
|
|
|
|
/** \brief Decode Priority
|
|
|
|
The function decodes an interrupt priority value with a given priority group to
|
|
preemptive priority value and subpriority value.
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
|
|
|
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
|
\param [in] PriorityGroup Used priority group.
|
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
|
*/
|
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
|
|
{
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
|
|
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
|
|
|
|
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
|
|
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
|
|
}
|
|
|
|
|
|
/** \brief System Reset
|
|
|
|
The function initiates a system reset request to reset the MCU.
|
|
*/
|
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
|
{
|
|
__DSB(); /* Ensure all outstanding memory accesses included
|
|
buffered write are completed before reset */
|
|
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
|
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
|
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
|
|
__DSB(); /* Ensure completion of memory access */
|
|
while(1); /* wait until reset */
|
|
}
|
|
|
|
/*@} end of CMSIS_Core_NVICFunctions */
|
|
|
|
|
|
|
|
/* ################################## SysTick function ############################################ */
|
|
/** \ingroup CMSIS_Core_FunctionInterface
|
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
|
\brief Functions that configure the System.
|
|
@{
|
|
*/
|
|
|
|
#if (__Vendor_SysTickConfig == 0)
|
|
|
|
/** \brief System Tick Configuration
|
|
|
|
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
|
Counter is in free running mode to generate periodic interrupts.
|
|
|
|
\param [in] ticks Number of ticks between two interrupts.
|
|
|
|
\return 0 Function succeeded.
|
|
\return 1 Function failed.
|
|
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
|
|
|
SysTick->LOAD = ticks - 1; /* set reload register */
|
|
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
|
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0); /* Function successful */
|
|
}
|
|
|
|
#endif
|
|
|
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
|
|
|
|
|
|
|
/* ##################################### Debug In/Output function ########################################### */
|
|
/** \ingroup CMSIS_Core_FunctionInterface
|
|
\defgroup CMSIS_core_DebugFunctions ITM Functions
|
|
\brief Functions that access the ITM debug interface.
|
|
@{
|
|
*/
|
|
|
|
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
|
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
|
|
|
|
|
/** \brief ITM Send Character
|
|
|
|
The function transmits a character via the ITM channel 0, and
|
|
\li Just returns when no debugger is connected that has booked the output.
|
|
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
|
|
|
|
\param [in] ch Character to transmit.
|
|
|
|
\returns Character to transmit.
|
|
*/
|
|
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
|
{
|
|
if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
|
|
(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
|
|
{
|
|
while (ITM->PORT[0].u32 == 0);
|
|
ITM->PORT[0].u8 = (uint8_t) ch;
|
|
}
|
|
return (ch);
|
|
}
|
|
|
|
|
|
/** \brief ITM Receive Character
|
|
|
|
The function inputs a character via the external variable \ref ITM_RxBuffer.
|
|
|
|
\return Received character.
|
|
\return -1 No character pending.
|
|
*/
|
|
__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
|
|
int32_t ch = -1; /* no character available */
|
|
|
|
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
|
|
ch = ITM_RxBuffer;
|
|
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
|
|
}
|
|
|
|
return (ch);
|
|
}
|
|
|
|
|
|
/** \brief ITM Check Character
|
|
|
|
The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
|
|
|
|
\return 0 No character available.
|
|
\return 1 Character available.
|
|
*/
|
|
__STATIC_INLINE int32_t ITM_CheckChar (void) {
|
|
|
|
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
|
|
return (0); /* no character available */
|
|
} else {
|
|
return (1); /* character available */
|
|
}
|
|
}
|
|
|
|
/*@} end of CMSIS_core_DebugFunctions */
|
|
|
|
#endif /* __CORE_CM3_H_DEPENDANT */
|
|
|
|
#endif /* __CMSIS_GENERIC */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|