761 lines
22 KiB
C
761 lines
22 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-5 SummerGift change to new framework
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*/
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#include "board.h"
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#define RT_USING_SPI
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#ifdef RT_USING_SPI
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#define BSP_USING_SPI1
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#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
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/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
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#include "drv_spi.h"
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#include "drv_config.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.spi"
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#include <drv_log.h>
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enum
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{
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#ifdef BSP_USING_SPI1
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SPI1_INDEX,
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#endif
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#ifdef BSP_USING_SPI2
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SPI2_INDEX,
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#endif
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#ifdef BSP_USING_SPI3
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SPI3_INDEX,
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#endif
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#ifdef BSP_USING_SPI4
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SPI4_INDEX,
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#endif
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#ifdef BSP_USING_SPI5
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SPI5_INDEX,
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#endif
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#ifdef BSP_USING_SPI6
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SPI6_INDEX,
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#endif
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};
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static struct stm32_spi_config spi_config[] =
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{
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#ifdef BSP_USING_SPI1
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SPI1_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_SPI2
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SPI2_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_SPI3
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SPI3_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_SPI4
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SPI4_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_SPI5
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SPI5_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_SPI6
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SPI6_BUS_CONFIG,
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#endif
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};
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static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])];
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static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
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{
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RT_ASSERT(spi_drv != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
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if (cfg->mode & RT_SPI_SLAVE)
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{
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spi_handle->Init.Mode = SPI_MODE_SLAVE;
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}
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else
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{
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spi_handle->Init.Mode = SPI_MODE_MASTER;
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}
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if (cfg->mode & RT_SPI_3WIRE)
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{
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spi_handle->Init.Direction = SPI_DIRECTION_1LINE;
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}
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else
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{
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spi_handle->Init.Direction = SPI_DIRECTION_2LINES;
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}
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if (cfg->data_width == 8)
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{
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spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;
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spi_handle->TxXferSize = 8;
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spi_handle->RxXferSize = 8;
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}
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else if (cfg->data_width == 16)
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{
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spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;
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}
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else
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{
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return RT_EIO;
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}
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if (cfg->mode & RT_SPI_CPHA)
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{
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spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;
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}
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else
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{
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spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;
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}
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if (cfg->mode & RT_SPI_CPOL)
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{
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spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
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}
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else
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{
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spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;
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}
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if (cfg->mode & RT_SPI_NO_CS)
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{
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spi_handle->Init.NSS = SPI_NSS_SOFT;
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}
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else
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{
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spi_handle->Init.NSS = SPI_NSS_SOFT;
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}
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uint32_t SPI_APB_CLOCK;
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SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();
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if (cfg->max_hz >= SPI_APB_CLOCK / 2)
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{
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
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}
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else if (cfg->max_hz >= SPI_APB_CLOCK / 4)
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{
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
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}
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else if (cfg->max_hz >= SPI_APB_CLOCK / 8)
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{
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
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}
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else if (cfg->max_hz >= SPI_APB_CLOCK / 16)
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{
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
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}
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else if (cfg->max_hz >= SPI_APB_CLOCK / 32)
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{
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
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}
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else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
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{
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
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}
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else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
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{
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
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}
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else
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{
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/* min prescaler 256 */
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spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
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}
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LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
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HAL_RCC_GetSysClockFreq(),
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SPI_APB_CLOCK,
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cfg->max_hz,
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spi_handle->Init.BaudRatePrescaler);
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if (cfg->mode & RT_SPI_MSB)
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{
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spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
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}
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else
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{
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spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;
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}
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spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
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spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi_handle->State = HAL_SPI_STATE_RESET;
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if (HAL_SPI_Init(spi_handle) != HAL_OK)
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{
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return RT_EIO;
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}
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#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
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SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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#endif
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__HAL_SPI_ENABLE(spi_handle);
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LOG_D("%s init done", spi_drv->config->bus_name);
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return RT_EOK;
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}
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#ifdef BSP_SPI_USING_DMA
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static uint8_t dummy = 0xFF;
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static void spi_dma_transfer_prepare(struct rt_spi_bus * spi_bus, struct rt_spi_message* message)
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{
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struct stm32_spi *spi_drv = rt_container_of(spi_bus, struct stm32_spi, spi_bus);
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DMA_HandleTypeDef * hdma_tx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_tx;
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DMA_HandleTypeDef * hdma_rx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_rx;
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HAL_DMA_DeInit(hdma_tx);
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HAL_DMA_DeInit(hdma_rx);
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/*
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* Check if the DMA Stream is disabled before enabling it.
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* Note that this step is useful when the same Stream is used multiple times.
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*/
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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while (hdma_tx->Instance->CR & DMA_SxCR_EN);
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while (hdma_rx->Instance->CR & DMA_SxCR_EN);
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#endif
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if(message->recv_buf != RT_NULL)
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{
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hdma_rx->Init.MemInc = DMA_MINC_ENABLE;
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}
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else
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{
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message->recv_buf = &dummy;
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hdma_rx->Init.MemInc = DMA_MINC_DISABLE;
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}
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HAL_DMA_Init(hdma_rx);
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__HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
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if(message->send_buf != RT_NULL)
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{
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hdma_tx->Init.MemInc = DMA_MINC_ENABLE;
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}
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else
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{
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dummy = 0xFF;
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message->send_buf = &dummy;
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hdma_tx->Init.MemInc = DMA_MINC_DISABLE;
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}
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HAL_DMA_Init(hdma_tx);
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/* link DMA with SPI */
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__HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
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LOG_D("%s RX Instance: %x, TX Instance: %x", spi_drv->config->bus_name, hdma_rx->Instance, hdma_tx->Instance);
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LOG_D("%s dma config done, TX dma_irq number: %d, RX dma_irq number: %d",
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spi_drv->config->bus_name,
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spi_drv->config->dma_tx.dma_irq,
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spi_drv->config->dma_rx.dma_irq);
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/* NVIC configuration for DMA transfer complete interrupt*/
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HAL_NVIC_SetPriority(spi_drv->config->dma_tx.dma_irq, 0, 1);
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HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx.dma_irq);
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/* NVIC configuration for DMA transfer complete interrupt*/
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HAL_NVIC_SetPriority(spi_drv->config->dma_rx.dma_irq, 0, 0);
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HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx.dma_irq);
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}
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#endif
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static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
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SPI_HandleTypeDef * spi_handle = &spi_drv->handle;
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struct stm32_hw_spi_cs *cs = device->parent.user_data;
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rt_int32_t length = message->length;
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rt_int32_t data_width = spi_drv->cfg->data_width;
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if (message->cs_take)
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{
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HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET);
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}
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#ifdef BSP_SPI_USING_DMA
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if(message->length > 32)
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{
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if(data_width <= 8)
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{
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HAL_StatusTypeDef state;
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LOG_D("%s dma transfer prepare and start", spi_drv->config->bus_name);
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LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
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spi_drv->config->bus_name,
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(uint32_t)message->send_buf,
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(uint32_t)message->recv_buf, message->length);
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spi_dma_transfer_prepare(device->bus, message);
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/* start once data exchange in DMA mode */
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state = HAL_SPI_TransmitReceive_DMA(spi_handle,
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(uint8_t*)message->send_buf,
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(uint8_t*)message->recv_buf,
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message->length);
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if (state != HAL_OK)
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{
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LOG_D("spi flash configuration error : %d", state);
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message->length = 0;
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//while(1);
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}
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else
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{
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LOG_D("%s dma transfer done", spi_drv->config->bus_name);
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}
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/* For simplicity reasons, this example is just waiting till the end of the
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transfer, but application may perform other tasks while transfer operation
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is ongoing. */
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while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
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LOG_D("%s get state done", spi_drv->config->bus_name);
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}
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else
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{
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// TODO
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}
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} else
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#endif
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{
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if (data_width == 8)
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{
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const rt_uint8_t * send_ptr = message->send_buf;
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rt_uint8_t * recv_ptr = message->recv_buf;
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while (length--)
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{
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rt_uint8_t data = ~0;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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/* send data once */
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while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
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*(volatile rt_uint8_t *)(&spi_handle->Instance->DR) = data;
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/* receive data once */
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#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
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SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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#endif
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while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
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data = *(volatile rt_uint8_t *)(&spi_handle->Instance->DR);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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} else
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{
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const rt_uint16_t * send_ptr = message->send_buf;
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rt_uint16_t * recv_ptr = message->recv_buf;
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while (length--)
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{
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rt_uint16_t data = ~0;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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/* send data once */
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while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
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*(volatile rt_uint16_t *)(&spi_handle->Instance->DR) = data;
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/* receive data once */
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#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
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SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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#endif
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while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
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data = *(volatile rt_uint16_t *)(&spi_handle->Instance->DR);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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}
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}
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/* Wait until Busy flag is reset before disabling SPI */
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while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_BSY) == SET);
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if (message->cs_release)
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{
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HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
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}
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return message->length;
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}
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static rt_err_t spi_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
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spi_drv->cfg = configuration;
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return stm32_spi_init(spi_drv, configuration);
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}
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static const struct rt_spi_ops stm_spi_ops =
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{
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.configure = spi_configure,
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.xfer = spixfer,
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};
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static int rt_hw_spi_bus_init(void)
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{
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rt_err_t result;
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for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
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{
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spi_bus_obj[i].config = &spi_config[i];
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spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
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spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
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#ifdef BSP_SPI_USING_DMA
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/* Configure the DMA handler for Transmission process */
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spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx.Instance;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx.channel;
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#elif defined(SOC_SERIES_STM32L4)
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spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx.request;
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#endif
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spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
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spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
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spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
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spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
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#endif
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spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx.Instance;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx.channel;
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#elif defined(SOC_SERIES_STM32L4)
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spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx.request;
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#endif
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spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
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spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
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spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
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spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
|
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
|
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
|
|
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
|
|
#endif
|
|
{
|
|
rt_uint32_t tmpreg = 0x00U;
|
|
#if defined(SOC_SERIES_STM32F1)
|
|
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
|
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
|
|
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
|
|
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
|
|
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
|
|
#endif
|
|
UNUSED(tmpreg); /* To avoid compiler warnings */
|
|
}
|
|
|
|
LOG_D("%s DMA clock init done", spi_config[i].bus_name);
|
|
#endif /* BSP_SPI_USING_DMA */
|
|
|
|
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
LOG_D("%s bus init done", spi_config[i].bus_name);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
/**
|
|
* Attach the spi device to SPI bus, this function must be used after initialization.
|
|
*/
|
|
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin)
|
|
{
|
|
RT_ASSERT(bus_name != RT_NULL);
|
|
RT_ASSERT(device_name != RT_NULL);
|
|
|
|
rt_err_t result;
|
|
struct rt_spi_device *spi_device;
|
|
struct stm32_hw_spi_cs *cs_pin;
|
|
|
|
/* initialize the cs pin && select the slave*/
|
|
GPIO_InitTypeDef GPIO_Initure;
|
|
GPIO_Initure.Pin = cs_gpio_pin;
|
|
GPIO_Initure.Mode = GPIO_MODE_OUTPUT_PP;
|
|
GPIO_Initure.Pull = GPIO_PULLUP;
|
|
GPIO_Initure.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
HAL_GPIO_Init(cs_gpiox, &GPIO_Initure);
|
|
HAL_GPIO_WritePin(cs_gpiox, cs_gpio_pin, GPIO_PIN_SET);
|
|
|
|
/* attach the device to spi bus*/
|
|
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
|
|
RT_ASSERT(spi_device != RT_NULL);
|
|
cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
|
|
RT_ASSERT(cs_pin != RT_NULL);
|
|
cs_pin->GPIOx = cs_gpiox;
|
|
cs_pin->GPIO_Pin = cs_gpio_pin;
|
|
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
|
|
|
|
if (result != RT_EOK)
|
|
{
|
|
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
|
|
}
|
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
LOG_D("%s attach to %s done", device_name, bus_name);
|
|
|
|
return result;
|
|
}
|
|
|
|
#if defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA)
|
|
/**
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI1_DMA_RX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI1_DMA_TX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_tx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
#if defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA)
|
|
/**
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI2_DMA_RX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_rx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI2_DMA_TX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
#if defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA)
|
|
/**
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI3_DMA_RX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_rx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI3_DMA_TX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_tx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
|
|
#if defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA)
|
|
/**
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI4_DMA_RX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_rx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI4_DMA_TX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_tx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
#if defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA)
|
|
/**
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI5_DMA_RX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_rx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI5_DMA_TX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_tx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
#if defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA)
|
|
/**
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI6_DMA_RX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_rx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SPI6_DMA_TX_IRQHandler(void)
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_tx);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
int rt_hw_spi_init(void)
|
|
{
|
|
return rt_hw_spi_bus_init();
|
|
}
|
|
INIT_BOARD_EXPORT(rt_hw_spi_init);
|
|
|
|
#endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4 || BSP_USING_SPI5 */
|
|
#endif /* RT_USING_SPI */
|