96 lines
2.2 KiB
C
96 lines
2.2 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2008-12-11 XuXinming first version
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* 2013-05-24 Grissiom port to RM48x50
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*/
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#include <rtthread.h>
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/**
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* @addtogroup RM48x50
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*/
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/*@{*/
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/**
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* this function will reset CPU
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*
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*/
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void rt_hw_cpu_reset()
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{
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}
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/**
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* this function will shutdown CPU
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*
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*/
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void rt_hw_cpu_shutdown()
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{
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rt_kprintf("shutdown...\n");
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while (1);
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}
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#ifdef __TI_COMPILER_VERSION__
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#ifdef RT_USING_CPU_FFS
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int __rt_ffs(int value)
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{
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if (value == 0)
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return value;
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__asm(" rsb r1, r0, #0");
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__asm(" and r1, r1, r0");
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__asm(" clz r1, r1");
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__asm(" rsb r0, r1, #32");
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}
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#endif
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void rt_hw_cpu_icache_enable()
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{
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__asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
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__asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable");
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__asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored");
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__asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache");
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__asm(" ISB");
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}
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void rt_hw_cpu_icache_disable()
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{
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__asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
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__asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable");
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__asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache");
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__asm(" ISB");
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}
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void rt_hw_cpu_dcache_enable()
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{
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__asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data");
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__asm(" ORR R1, R1, #0x1 <<2");
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__asm(" DSB");
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__asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache");
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__asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache");
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}
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void rt_hw_cpu_dcache_disable()
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{
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/* FIXME: Clean entire data cache. This routine depends on the data cache
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* size. It can be omitted if it is known that the data cache has no dirty
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* data. */
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__asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
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__asm(" BIC r1, r1, #0x1 <<2");
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__asm(" DSB");
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__asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache");
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}
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#elif __GNUC__
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int __rt_ffs(int value)
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{
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return __builtin_ffs(value);
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}
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#endif
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/*@}*/
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