980 lines
35 KiB
C
980 lines
35 KiB
C
//*****************************************************************************
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//
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// adc.c - Driver for the ADC.
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//
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// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup adc_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_adc.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_types.h"
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#include "driverlib/adc.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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//*****************************************************************************
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//
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// These defines are used by the ADC driver to simplify access to the ADC
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// sequencer's registers.
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//
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//*****************************************************************************
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#define ADC_SEQ (ADC_O_SSMUX0)
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#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
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#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
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#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
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#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
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#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
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//*****************************************************************************
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//
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// The currently configured software oversampling factor for each of the ADC
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// sequencers.
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//
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//*****************************************************************************
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static unsigned char g_pucOversampleFactor[3];
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//*****************************************************************************
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//
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//! Registers an interrupt handler for an ADC interrupt.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! ADC sample sequence interrupt occurs.
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//!
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//! This function sets the handler to be called when a sample sequence
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//! interrupt occurs. This will enable the global interrupt in the interrupt
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//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
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//! is the interrupt handler's responsibility to clear the interrupt source via
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//! ADCIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
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void (*pfnHandler)(void))
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{
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unsigned long ulInt;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Determine the interrupt to register based on the sequence number.
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//
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ulInt = INT_ADC0 + ulSequenceNum;
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//
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// Register the interrupt handler.
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//
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IntRegister(ulInt, pfnHandler);
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//
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// Enable the timer interrupt.
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//
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IntEnable(ulInt);
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}
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//*****************************************************************************
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//
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//! Unregisters the interrupt handler for an ADC interrupt.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//!
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//! This function unregisters the interrupt handler. This will disable the
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//! global interrupt in the interrupt controller; the sequence interrupt must
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//! be disabled via ADCIntDisable().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
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{
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unsigned long ulInt;
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//
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// Check the arguments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Determine the interrupt to unregister based on the sequence number.
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//
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ulInt = INT_ADC0 + ulSequenceNum;
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//
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// Disable the interrupt.
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//
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IntDisable(ulInt);
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//
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// Unregister the interrupt handler.
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//
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IntUnregister(ulInt);
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}
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//*****************************************************************************
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//
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//! Disables a sample sequence interrupt.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//!
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//! This function disables the requested sample sequence interrupt.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Disable this sample sequence interrupt.
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//
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HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
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}
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//*****************************************************************************
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//
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//! Enables a sample sequence interrupt.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//!
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//! This function enables the requested sample sequence interrupt. Any
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//! outstanding interrupts are cleared before enabling the sample sequence
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//! interrupt.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Clear any outstanding interrupts on this sample sequence.
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//
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HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
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//
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// Enable this sample sequence interrupt.
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//
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HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
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}
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//*****************************************************************************
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//
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//! Gets the current interrupt status.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//! \param bMasked is false if the raw interrupt status is required and true if
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//! the masked interrupt status is required.
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//!
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//! This returns the interrupt status for the specified sample sequence.
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//! Either the raw interrupt status or the status of interrupts that are
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//! allowed to reflect to the processor can be returned.
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//!
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//! \return The current raw or masked interrupt status.
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//
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//*****************************************************************************
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unsigned long
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ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
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tBoolean bMasked)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Return either the interrupt status or the raw interrupt status as
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// requested.
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//
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if(bMasked)
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{
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return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));
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}
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else
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{
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return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));
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}
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}
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//*****************************************************************************
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//
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//! Clears sample sequence interrupt source.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//!
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//! The specified sample sequence interrupt is cleared, so that it no longer
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//! asserts. This must be done in the interrupt handler to keep it from being
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//! called again immediately upon exit.
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//!
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//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
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//! several clock cycles before the interrupt source is actually cleared.
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//! Therefore, it is recommended that the interrupt source be cleared early in
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//! the interrupt handler (as opposed to the very last action) to avoid
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//! returning from the interrupt handler before the interrupt source is
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//! actually cleared. Failure to do so may result in the interrupt handler
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//! being immediately reentered (since NVIC still sees the interrupt source
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//! asserted).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
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{
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//
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// Check the arugments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Clear the interrupt.
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//
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HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
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}
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//*****************************************************************************
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//
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//! Enables a sample sequence.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//!
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//! Allows the specified sample sequence to be captured when its trigger is
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//! detected. A sample sequence must be configured before it is enabled.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
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{
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//
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// Check the arugments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Enable the specified sequence.
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//
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HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
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}
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//*****************************************************************************
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//
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//! Disables a sample sequence.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//!
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//! Prevents the specified sample sequence from being captured when its trigger
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//! is detected. A sample sequence should be disabled before it is configured.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
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{
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//
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// Check the arugments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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//
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// Disable the specified sequences.
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//
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HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
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}
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//*****************************************************************************
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//
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//! Configures the trigger source and priority of a sample sequence.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//! \param ulTrigger is the trigger source that initiates the sample sequence;
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//! must be one of the \b ADC_TRIGGER_* values.
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//! \param ulPriority is the relative priority of the sample sequence with
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//! respect to the other sample sequences.
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//!
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//! This function configures the initiation criteria for a sample sequence.
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//! Valid sample sequences range from zero to three; sequence zero will capture
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//! up to eight samples, sequences one and two will capture up to four samples,
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//! and sequence three will capture a single sample. The trigger condition and
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//! priority (with respect to other sample sequence execution) is set.
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//!
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//! The \e ulTrigger parameter can take on the following values:
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//!
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//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
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//! ADCProcessorTrigger() function.
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//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
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//! comparator; configured with ComparatorConfigure().
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//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
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//! comparator; configured with ComparatorConfigure().
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//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
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//! comparator; configured with ComparatorConfigure().
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//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
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//! B4 pin.
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//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
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//! TimerControlTrigger().
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//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
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//! configured with PWMGenIntTrigEnable().
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//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
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//! configured with PWMGenIntTrigEnable().
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//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
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//! configured with PWMGenIntTrigEnable().
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//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
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//! sample sequence to capture repeatedly (so long as
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//! there is not a higher priority source active).
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//!
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//! Note that not all trigger sources are available on all Stellaris family
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//! members; consult the data sheet for the device in question to determine the
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//! availability of triggers.
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//!
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//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents
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//! the highest priority and 3 the lowest. Note that when programming the
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//! priority among a set of sample sequences, each must have unique priority;
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//! it is up to the caller to guarantee the uniqueness of the priorities.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
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unsigned long ulTrigger, unsigned long ulPriority)
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{
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//
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// Check the arugments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
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(ulTrigger == ADC_TRIGGER_COMP0) ||
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(ulTrigger == ADC_TRIGGER_COMP1) ||
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(ulTrigger == ADC_TRIGGER_COMP2) ||
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(ulTrigger == ADC_TRIGGER_EXTERNAL) ||
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(ulTrigger == ADC_TRIGGER_TIMER) ||
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(ulTrigger == ADC_TRIGGER_PWM0) ||
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(ulTrigger == ADC_TRIGGER_PWM1) ||
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(ulTrigger == ADC_TRIGGER_PWM2) ||
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(ulTrigger == ADC_TRIGGER_ALWAYS));
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ASSERT(ulPriority < 4);
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//
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// Compute the shift for the bits that control this sample sequence.
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//
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ulSequenceNum *= 4;
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//
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// Set the trigger event for this sample sequence.
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//
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HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
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~(0xf << ulSequenceNum)) |
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((ulTrigger & 0xf) << ulSequenceNum));
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//
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// Set the priority for this sample sequence.
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//
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HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
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~(0xf << ulSequenceNum)) |
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((ulPriority & 0x3) << ulSequenceNum));
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}
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//*****************************************************************************
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//
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//! Configure a step of the sample sequencer.
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//!
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//! \param ulBase is the base address of the ADC module.
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//! \param ulSequenceNum is the sample sequence number.
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//! \param ulStep is the step to be configured.
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//! \param ulConfig is the configuration of this step; must be a logical OR of
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//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
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//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).
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//!
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//! This function will set the configuration of the ADC for one step of a
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//! sample sequence. The ADC can be configured for single-ended or
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//! differential operation (the \b ADC_CTL_D bit selects differential
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//! operation when set), the channel to be sampled can be chosen (the
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//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature
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//! sensor can be selected (the \b ADC_CTL_TS bit). Additionally, this step
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//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it
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//! can be configured to cause an interrupt when the step is complete (the
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//! \b ADC_CTL_IE bit). The configuration is used by the ADC at the
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//! appropriate time when the trigger for this sequence occurs.
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//!
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//! The \e ulStep parameter determines the order in which the samples are
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//! captured by the ADC when the trigger occurs. It can range from zero to
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//! seven for the first sample sequence, from zero to three for the second and
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//! third sample sequence, and can only be zero for the fourth sample sequence.
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//!
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//! Differential mode only works with adjacent channel pairs (for example, 0
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//! and 1). The channel select must be the number of the channel pair to
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//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
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//! and 3) or undefined results will be returned by the ADC. Additionally, if
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//! differential mode is selected when the temperature sensor is being sampled,
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//! undefined results will be returned by the ADC.
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//!
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//! It is the responsibility of the caller to ensure that a valid configuration
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//! is specified; this function does not check the validity of the specified
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//! configuration.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
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unsigned long ulStep, unsigned long ulConfig)
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{
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//
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// Check the arugments.
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//
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ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
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ASSERT(ulSequenceNum < 4);
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ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
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((ulSequenceNum == 1) && (ulStep < 4)) ||
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((ulSequenceNum == 2) && (ulStep < 4)) ||
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((ulSequenceNum == 3) && (ulStep < 1)));
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//
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// Get the offset of the sequence to be configured.
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//
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ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
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//
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// Compute the shift for the bits that control this step.
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//
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ulStep *= 4;
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//
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// Set the analog mux value for this step.
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//
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HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
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~(0x0000000f << ulStep)) |
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((ulConfig & 0x0f) << ulStep));
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//
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// Set the control value for this step.
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//
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HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
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~(0x0000000f << ulStep)) |
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(((ulConfig & 0xf0) >> 4) << ulStep));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Determines if a sample sequence overflow occurred.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//!
|
|
//! This determines if a sample sequence overflow has occurred. This will
|
|
//! happen if the captured samples are not read from the FIFO before the next
|
|
//! trigger occurs.
|
|
//!
|
|
//! \return Returns zero if there was not an overflow, and non-zero if there
|
|
//! was.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 4);
|
|
|
|
//
|
|
// Determine if there was an overflow on this sequence.
|
|
//
|
|
return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears the overflow condition on a sample sequence.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//!
|
|
//! This will clear an overflow condition on one of the sample sequences. The
|
|
//! overflow condition must be cleared in order to detect a subsequent overflow
|
|
//! condition (it otherwise causes no harm).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 4);
|
|
|
|
//
|
|
// Clear the overflow condition for this sequence.
|
|
//
|
|
HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Determines if a sample sequence underflow occurred.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//!
|
|
//! This determines if a sample sequence underflow has occurred. This will
|
|
//! happen if too many samples are read from the FIFO.
|
|
//!
|
|
//! \return Returns zero if there was not an underflow, and non-zero if there
|
|
//! was.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 4);
|
|
|
|
//
|
|
// Determine if there was an underflow on this sequence.
|
|
//
|
|
return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears the underflow condition on a sample sequence.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//!
|
|
//! This will clear an underflow condition on one of the sample sequences. The
|
|
//! underflow condition must be cleared in order to detect a subsequent
|
|
//! underflow condition (it otherwise causes no harm).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 4);
|
|
|
|
//
|
|
// Clear the underflow condition for this sequence.
|
|
//
|
|
HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the captured data for a sample sequence.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//! \param pulBuffer is the address where the data is stored.
|
|
//!
|
|
//! This function copies data from the specified sample sequence output FIFO to
|
|
//! a memory resident buffer. The number of samples available in the hardware
|
|
//! FIFO are copied into the buffer, which is assumed to be large enough to
|
|
//! hold that many samples. This will only return the samples that are
|
|
//! presently available, which may not be the entire sample sequence if it is
|
|
//! in the process of being executed.
|
|
//!
|
|
//! \return Returns the number of samples copied to the buffer.
|
|
//
|
|
//*****************************************************************************
|
|
long
|
|
ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
|
|
unsigned long *pulBuffer)
|
|
{
|
|
unsigned long ulCount;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 4);
|
|
|
|
//
|
|
// Get the offset of the sequence to be read.
|
|
//
|
|
ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
|
|
|
|
//
|
|
// Read samples from the FIFO until it is empty.
|
|
//
|
|
ulCount = 0;
|
|
while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8))
|
|
{
|
|
//
|
|
// Read the FIFO and copy it to the destination.
|
|
//
|
|
*pulBuffer++ = HWREG(ulBase + ADC_SSFIFO);
|
|
|
|
//
|
|
// Increment the count of samples read.
|
|
//
|
|
ulCount++;
|
|
}
|
|
|
|
//
|
|
// Return the number of samples read.
|
|
//
|
|
return(ulCount);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Causes a processor trigger for a sample sequence.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//!
|
|
//! This function triggers a processor-initiated sample sequence if the sample
|
|
//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 4);
|
|
|
|
//
|
|
// Generate a processor trigger for this sample sequence.
|
|
//
|
|
HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the software oversampling factor of the ADC.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//! \param ulFactor is the number of samples to be averaged.
|
|
//!
|
|
//! This function configures the software oversampling for the ADC, which can
|
|
//! be used to provide better resolution on the sampled data. Oversampling is
|
|
//! accomplished by averaging multiple samples from the same analog input.
|
|
//! Three different oversampling rates are supported; 2x, 4x, and 8x.
|
|
//!
|
|
//! Oversampling is only supported on the sample sequencers that are more than
|
|
//! one sample in depth (that is, the fourth sample sequencer is not
|
|
//! supported). Oversampling by 2x (for example) divides the depth of the
|
|
//! sample sequencer by two; so 2x oversampling on the first sample sequencer
|
|
//! can only provide four samples per trigger. This also means that 8x
|
|
//! oversampling is only available on the first sample sequencer.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
ADCSoftwareOversampleConfigure(unsigned long ulBase,
|
|
unsigned long ulSequenceNum,
|
|
unsigned long ulFactor)
|
|
{
|
|
unsigned long ulValue;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 3);
|
|
ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
|
|
((ulSequenceNum == 0) || (ulFactor != 8)));
|
|
|
|
//
|
|
// Convert the oversampling factor to a shift factor.
|
|
//
|
|
for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
|
|
{
|
|
}
|
|
|
|
//
|
|
// Save the sfiht factor.
|
|
//
|
|
g_pucOversampleFactor[ulSequenceNum] = ulValue;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures a step of the software oversampled sequencer.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//! \param ulStep is the step to be configured.
|
|
//! \param ulConfig is the configuration of this step.
|
|
//!
|
|
//! This function configures a step of the sample sequencer when using the
|
|
//! software oversampling feature. The number of steps available depends on
|
|
//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
|
|
//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
|
|
unsigned long ulSequenceNum,
|
|
unsigned long ulStep,
|
|
unsigned long ulConfig)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 3);
|
|
ASSERT(((ulSequenceNum == 0) &&
|
|
(ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
|
|
(ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
|
|
|
|
//
|
|
// Get the offset of the sequence to be configured.
|
|
//
|
|
ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
|
|
|
|
//
|
|
// Compute the shift for the bits that control this step.
|
|
//
|
|
ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
|
|
|
|
//
|
|
// Loop through the hardware steps that make up this step of the software
|
|
// oversampled sequence.
|
|
//
|
|
for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
|
|
ulSequenceNum; ulSequenceNum--)
|
|
{
|
|
//
|
|
// Set the analog mux value for this step.
|
|
//
|
|
HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
|
|
~(0x0000000f << ulStep)) |
|
|
((ulConfig & 0x0f) << ulStep));
|
|
|
|
//
|
|
// Set the control value for this step.
|
|
//
|
|
HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
|
|
~(0x0000000f << ulStep)) |
|
|
(((ulConfig & 0xf0) >> 4) << ulStep));
|
|
if(ulSequenceNum != 1)
|
|
{
|
|
HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
|
|
ADC_SSCTL0_END0) << ulStep);
|
|
}
|
|
|
|
//
|
|
// Go to the next hardware step.
|
|
//
|
|
ulStep += 4;
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the captured data for a sample sequence using software oversampling.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulSequenceNum is the sample sequence number.
|
|
//! \param pulBuffer is the address where the data is stored.
|
|
//! \param ulCount is the number of samples to be read.
|
|
//!
|
|
//! This function copies data from the specified sample sequence output FIFO to
|
|
//! a memory resident buffer with software oversampling applied. The requested
|
|
//! number of samples are copied into the data buffer; if there are not enough
|
|
//! samples in the hardware FIFO to satisfy this many oversampled data items
|
|
//! then incorrect results will be returned. It is the caller's responsibility
|
|
//! to read only the samples that are available and wait until enough data is
|
|
//! available, for example as a result of receiving an interrupt.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
|
|
unsigned long *pulBuffer, unsigned long ulCount)
|
|
{
|
|
unsigned long ulIdx, ulAccum;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(ulSequenceNum < 3);
|
|
ASSERT(((ulSequenceNum == 0) &&
|
|
(ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
|
|
(ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
|
|
|
|
//
|
|
// Get the offset of the sequence to be read.
|
|
//
|
|
ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
|
|
|
|
//
|
|
// Read the samples from the FIFO until it is empty.
|
|
//
|
|
while(ulCount--)
|
|
{
|
|
//
|
|
// Compute the sum of the samples.
|
|
//
|
|
ulAccum = 0;
|
|
for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
|
|
{
|
|
//
|
|
// Read the FIFO and add it to the accumulator.
|
|
//
|
|
ulAccum += HWREG(ulBase + ADC_SSFIFO);
|
|
}
|
|
|
|
//
|
|
// Write the averaged sample to the output buffer.
|
|
//
|
|
*pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Configures the hardware oversampling factor of the ADC.
|
|
//!
|
|
//! \param ulBase is the base address of the ADC module.
|
|
//! \param ulFactor is the number of samples to be averaged.
|
|
//!
|
|
//! This function configures the hardware oversampling for the ADC, which can
|
|
//! be used to provide better resolution on the sampled data. Oversampling is
|
|
//! accomplished by averaging multiple samples from the same analog input. Six
|
|
//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
|
|
//! Specifying an oversampling factor of zero will disable hardware
|
|
//! oversampling.
|
|
//!
|
|
//! Hardware oversampling applies uniformly to all sample sequencers. It does
|
|
//! not reduce the depth of the sample sequencers like the software
|
|
//! oversampling APIs; each sample written into the sample sequence FIFO is a
|
|
//! fully oversampled analog input reading.
|
|
//!
|
|
//! Enabling hardware averaging increases the precision of the ADC at the cost
|
|
//! of throughput. For example, enabling 4x oversampling reduces the
|
|
//! throughput of a 250 Ksps ADC to 62.5 Ksps.
|
|
//!
|
|
//! \note Hardware oversampling is available beginning with Rev C0 of the
|
|
//! Stellaris microcontroller.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
|
|
{
|
|
unsigned long ulValue;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
|
|
ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
|
|
(ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
|
|
(ulFactor == 64)));
|
|
|
|
//
|
|
// Convert the oversampling factor to a shift factor.
|
|
//
|
|
for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
|
|
{
|
|
}
|
|
|
|
//
|
|
// Write the shift factor to the ADC to configure the hardware oversampler.
|
|
//
|
|
HWREG(ulBase + ADC_O_SAC) = ulValue;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|