2168ed8e7d
PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <2991707448@qq.com>
147 lines
3.3 KiB
C
147 lines
3.3 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-24 GuEe-GUI first version
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*/
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#include <drivers/pci_msi.h>
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#define DBG_TAG "pci.msi.irq"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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static struct rt_spinlock msi_irq_map_lock = {};
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static RT_BITMAP_DECLARE(msi_irq_map, MAX_HANDLERS) = {};
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rt_err_t rt_pci_msi_setup_irqs(struct rt_pci_device *pdev, int nvec, int type)
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{
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int irq, index = 0, irq_nr = 0;
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rt_err_t err = RT_EOK;
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struct rt_pic_irq *pirq;
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struct rt_pic *msi_pic;
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struct rt_pci_msi_desc *desc;
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if (!pdev)
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{
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return -RT_EINVAL;
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}
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msi_pic = pdev->msi_pic;
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if (type == PCIY_MSI)
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{
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int last_irq = -1;
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rt_size_t irq_nr;
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desc = rt_pci_msi_first_desc(pdev);
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irq_nr = 1 << desc->msi.cap.multi_msg_use;
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rt_hw_spin_lock(&msi_irq_map_lock.lock);
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_retry:
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for (int i = 0; i < irq_nr; ++i)
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{
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if ((irq = msi_pic->ops->irq_alloc_msi(msi_pic, desc)) < 0)
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{
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err = irq;
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LOG_E("Setup %s[%d] IRQ error = %s", "MSI", i, rt_strerror(err));
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break;
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}
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if (last_irq >= 0 && last_irq + 1 != irq)
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{
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for (int idx = 0; idx < i; ++i, --last_irq)
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{
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rt_bitmap_set_bit(msi_irq_map, last_irq);
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}
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last_irq = irq;
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goto _retry;
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}
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last_irq = irq;
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}
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if (!err)
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{
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/* Get the first irq */
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desc->irq = irq - irq_nr;
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}
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rt_bitmap_for_each_set_bit(msi_irq_map, irq, MAX_HANDLERS)
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{
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msi_pic->ops->irq_free_msi(msi_pic, irq);
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/* Free bit so the next user doesn't need to bzero */
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rt_bitmap_clear_bit(msi_irq_map, irq);
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}
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rt_hw_spin_unlock(&msi_irq_map_lock.lock);
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if (!err)
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{
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for (int idx = 0; idx < nvec; ++idx)
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{
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pirq = rt_pic_find_pirq(msi_pic, irq + idx);
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pirq->msi_desc = desc;
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msi_pic->ops->irq_compose_msi_msg(pirq, &desc->msg);
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rt_pci_msi_write_msg(desc, &desc->msg);
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}
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}
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}
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else if (type == PCIY_MSIX)
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{
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rt_pci_msi_for_each_desc(pdev, desc)
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{
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if ((irq = msi_pic->ops->irq_alloc_msi(msi_pic, desc)) < 0)
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{
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err = irq;
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LOG_E("Setup %s[%d] IRQ error = %s", "MSI-X",
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desc->msix.index, rt_strerror(err));
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break;
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}
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desc->irq = irq;
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pirq = rt_pic_find_pirq(msi_pic, irq);
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pirq->msi_desc = desc;
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msi_pic->ops->irq_compose_msi_msg(pirq, &desc->msg);
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rt_pci_msi_write_msg(desc, &desc->msg);
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++irq_nr;
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}
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if (err)
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{
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rt_pci_msi_for_each_desc(pdev, desc)
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{
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if (index >= irq_nr)
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{
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break;
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}
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msi_pic->ops->irq_free_msi(msi_pic, desc->irq);
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++index;
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}
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}
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}
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else
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{
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err = -RT_EINVAL;
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}
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return err;
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}
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