252 lines
6.4 KiB
C
252 lines
6.4 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-11-28 GuEe-GUI first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <cpuport.h>
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#include <mmu.h>
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#define ARCH_SECTION_SHIFT 21
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#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT)
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#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1)
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#define ARCH_PAGE_SHIFT 12
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#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT)
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#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
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#define MMU_LEVEL_MASK 0x1ffUL
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#define MMU_LEVEL_SHIFT 9
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#define MMU_ADDRESS_BITS 39
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#define MMU_ADDRESS_MASK 0x0000fffffffff000UL
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#define MMU_ATTRIB_MASK 0xfff0000000000ffcUL
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#define MMU_TYPE_MASK 3UL
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#define MMU_TYPE_USED 1UL
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#define MMU_TYPE_BLOCK 1UL
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#define MMU_TYPE_TABLE 3UL
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#define MMU_TYPE_PAGE 3UL
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#define MMU_TBL_BLOCK_2M_LEVEL 2
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#define MMU_TBL_PAGE_NR_MAX 32
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/* only map 4G io/memory */
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static volatile unsigned long MMUTable[512] __attribute__((aligned(4096)));
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static volatile struct
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{
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unsigned long entry[512];
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} MMUPage[MMU_TBL_PAGE_NR_MAX] __attribute__((aligned(4096)));
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static unsigned long _kernel_free_page(void)
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{
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static unsigned long i = 0;
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if (i >= MMU_TBL_PAGE_NR_MAX)
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{
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return RT_NULL;
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}
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++i;
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return (unsigned long)&MMUPage[i - 1].entry;
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}
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static int _kenrel_map_2M(unsigned long *tbl, unsigned long va, unsigned long pa, unsigned long attr)
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{
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int level;
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unsigned long *cur_lv_tbl = tbl;
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unsigned long page;
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unsigned long off;
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int level_shift = MMU_ADDRESS_BITS;
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if (va & ARCH_SECTION_MASK)
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{
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return MMU_MAP_ERROR_VANOTALIGN;
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}
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if (pa & ARCH_SECTION_MASK)
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{
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return MMU_MAP_ERROR_PANOTALIGN;
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}
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for (level = 0; level < MMU_TBL_BLOCK_2M_LEVEL; ++level)
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{
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off = (va >> level_shift);
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off &= MMU_LEVEL_MASK;
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if (!(cur_lv_tbl[off] & MMU_TYPE_USED))
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{
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page = _kernel_free_page();
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if (!page)
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{
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return MMU_MAP_ERROR_NOPAGE;
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}
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rt_memset((char *)page, 0, ARCH_PAGE_SIZE);
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)page, ARCH_PAGE_SIZE);
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cur_lv_tbl[off] = page | MMU_TYPE_TABLE;
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *));
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}
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else
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{
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page = cur_lv_tbl[off];
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page &= MMU_ADDRESS_MASK;
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}
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page = cur_lv_tbl[off];
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if ((page & MMU_TYPE_MASK) == MMU_TYPE_BLOCK)
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{
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/* is block! error! */
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return MMU_MAP_ERROR_CONFLICT;
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}
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/* next level */
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cur_lv_tbl = (unsigned long *)(page & MMU_ADDRESS_MASK);
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level_shift -= MMU_LEVEL_SHIFT;
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}
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attr &= MMU_ATTRIB_MASK;
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pa |= (attr | MMU_TYPE_BLOCK);
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off = (va >> ARCH_SECTION_SHIFT);
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off &= MMU_LEVEL_MASK;
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cur_lv_tbl[off] = pa;
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cur_lv_tbl + off, sizeof(void *));
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return 0;
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}
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int rt_hw_mmu_setmtt(unsigned long vaddr_start, unsigned long vaddr_end,
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unsigned long paddr_start, unsigned long attr)
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{
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int ret = -1;
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int i;
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unsigned long count;
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unsigned long map_attr = MMU_MAP_CUSTOM(MMU_AP_KAUN, attr);
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if (vaddr_start > vaddr_end)
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{
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goto end;
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}
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if (vaddr_start % ARCH_SECTION_SIZE)
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{
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vaddr_start = (vaddr_start / ARCH_SECTION_SIZE) * ARCH_SECTION_SIZE;
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}
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if (paddr_start % ARCH_SECTION_SIZE)
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{
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paddr_start = (paddr_start / ARCH_SECTION_SIZE) * ARCH_SECTION_SIZE;
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}
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if (vaddr_end % ARCH_SECTION_SIZE)
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{
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vaddr_end = (vaddr_end / ARCH_SECTION_SIZE + 1) * ARCH_SECTION_SIZE;
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}
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count = (vaddr_end - vaddr_start) >> ARCH_SECTION_SHIFT;
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for (i = 0; i < count; i++)
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{
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ret = _kenrel_map_2M((void *)MMUTable, vaddr_start, paddr_start, map_attr);
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vaddr_start += ARCH_SECTION_SIZE;
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paddr_start += ARCH_SECTION_SIZE;
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if (ret != 0)
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{
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goto end;
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}
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}
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end:
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return ret;
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}
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void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_size_t desc_nr)
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{
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rt_memset((void *)MMUTable, 0, sizeof(MMUTable));
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rt_memset((void *)MMUPage, 0, sizeof(MMUPage));
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/* set page table */
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for (; desc_nr > 0; --desc_nr)
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{
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rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, mdesc->paddr_start, mdesc->attr);
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++mdesc;
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}
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rt_hw_dcache_flush_range((unsigned long)MMUTable, sizeof(MMUTable));
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}
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void rt_hw_mmu_tlb_invalidate(void)
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{
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__asm__ volatile (
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"tlbi vmalle1\n\r"
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"dsb sy\n\r"
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"isb sy\n\r"
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"ic ialluis\n\r"
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"dsb sy\n\r"
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"isb sy");
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}
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void rt_hw_mmu_init(void)
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{
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unsigned long reg_val;
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reg_val = 0x00447fUL;
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__asm__ volatile("msr mair_el1, %0"::"r"(reg_val));
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rt_hw_isb();
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reg_val = (16UL << 0) /* t0sz 48bit */
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| (0UL << 6) /* reserved */
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| (0UL << 7) /* epd0 */
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| (3UL << 8) /* t0 wb cacheable */
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| (3UL << 10) /* inner shareable */
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| (2UL << 12) /* t0 outer shareable */
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| (0UL << 14) /* t0 4K */
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| (16UL << 16) /* t1sz 48bit */
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| (0UL << 22) /* define asid use ttbr0.asid */
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| (0UL << 23) /* epd1 */
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| (3UL << 24) /* t1 inner wb cacheable */
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| (3UL << 26) /* t1 outer wb cacheable */
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| (2UL << 28) /* t1 outer shareable */
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| (2UL << 30) /* t1 4k */
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| (1UL << 32) /* 001b 64GB PA */
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| (0UL << 35) /* reserved */
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| (1UL << 36) /* as: 0:8bit 1:16bit */
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| (0UL << 37) /* tbi0 */
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| (0UL << 38); /* tbi1 */
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__asm__ volatile("msr tcr_el1, %0"::"r"(reg_val));
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rt_hw_isb();
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__asm__ volatile ("mrs %0, sctlr_el1":"=r"(reg_val));
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reg_val |= 1 << 2; /* enable dcache */
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reg_val |= 1 << 0; /* enable mmu */
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__asm__ volatile (
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"msr ttbr0_el1, %0\n\r"
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"msr sctlr_el1, %1\n\r"
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"dsb sy\n\r"
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"isb sy\n\r"
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::"r"(MMUTable), "r"(reg_val) :"memory");
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rt_hw_mmu_tlb_invalidate();
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}
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int rt_hw_mmu_map(unsigned long addr, unsigned long size, unsigned long attr)
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{
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int ret;
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rt_ubase_t level;
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level = rt_hw_interrupt_disable();
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ret = rt_hw_mmu_setmtt(addr, addr + size, addr, attr);
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rt_hw_interrupt_enable(level);
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return ret;
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}
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