382 lines
8.0 KiB
C
382 lines
8.0 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard first version
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* 2018-11-22 Jesven add smp support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "interrupt.h"
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#include "gic.h"
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#include "gicv3.h"
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#include "armv8.h"
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#include "mmu.h"
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#include "cpuport.h"
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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/* Those variables will be accessed in ISR, so we need to share them. */
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rt_ubase_t rt_interrupt_from_thread = 0;
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rt_ubase_t rt_interrupt_to_thread = 0;
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rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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extern int system_vectors;
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void rt_hw_vector_init(void)
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{
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rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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/* initialize vector table */
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rt_hw_vector_init();
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/* initialize exceptions table */
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rt_memset(isr_table, 0x00, sizeof(isr_table));
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#ifndef BSP_USING_GIC
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/* mask all of interrupts */
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IRQ_DISABLE_BASIC = 0x000000ff;
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IRQ_DISABLE1 = 0xffffffff;
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IRQ_DISABLE2 = 0xffffffff;
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#else
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/* initialize ARM GIC */
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arm_gic_dist_init(0, platform_get_gic_dist_base(), GIC_IRQ_START);
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arm_gic_cpu_init(0, platform_get_gic_cpu_base());
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#ifdef BSP_USING_GICV3
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arm_gic_redist_init(0, platform_get_gic_redist_base());
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#endif
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#endif
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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#ifndef BSP_USING_GIC
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if (vector < 32)
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{
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IRQ_DISABLE1 = (1 << vector);
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}
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else if (vector < 64)
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{
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vector = vector % 32;
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IRQ_DISABLE2 = (1 << vector);
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}
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else
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{
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vector = vector - 64;
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IRQ_DISABLE_BASIC = (1 << vector);
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}
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#else
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arm_gic_mask(0, vector);
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#endif
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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#ifndef BSP_USING_GIC
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if (vector < 32)
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{
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IRQ_ENABLE1 = (1 << vector);
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}
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else if (vector < 64)
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{
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vector = vector % 32;
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IRQ_ENABLE2 = (1 << vector);
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}
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else
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{
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vector = vector - 64;
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IRQ_ENABLE_BASIC = (1 << vector);
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}
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#else
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arm_gic_umask(0, vector);
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#endif
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}
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/**
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* This function returns the active interrupt number.
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* @param none
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*/
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int rt_hw_interrupt_get_irq(void)
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{
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#ifdef BSP_USING_GIC
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return arm_gic_get_active_irq(0);
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#else
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return 0;
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#endif
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}
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/**
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* This function acknowledges the interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_ack(int vector)
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{
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#ifdef BSP_USING_GIC
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arm_gic_ack(0, vector);
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#endif
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}
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/**
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* This function set interrupt CPU targets.
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* @param vector: the interrupt number
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* cpu_mask: target cpus mask, one bit for one core
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*/
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void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask)
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{
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#ifdef BSP_USING_GIC
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arm_gic_set_cpu(0, vector, cpu_mask);
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#endif
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}
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/**
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* This function get interrupt CPU targets.
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* @param vector: the interrupt number
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* @return target cpus mask, one bit for one core
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*/
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unsigned int rt_hw_interrupt_get_target_cpus(int vector)
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{
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#ifdef BSP_USING_GIC
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return arm_gic_get_target_cpu(0, vector);
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#else
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return -RT_ERROR;
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#endif
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}
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/**
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* This function set interrupt triger mode.
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* @param vector: the interrupt number
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* mode: interrupt triger mode; 0: level triger, 1: edge triger
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*/
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void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode)
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{
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#ifdef BSP_USING_GIC
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arm_gic_set_configuration(0, vector, mode);
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#endif
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}
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/**
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* This function get interrupt triger mode.
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* @param vector: the interrupt number
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* @return interrupt triger mode; 0: level triger, 1: edge triger
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*/
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unsigned int rt_hw_interrupt_get_triger_mode(int vector)
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{
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#ifdef BSP_USING_GIC
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return arm_gic_get_configuration(0, vector);
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#else
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return -RT_ERROR;
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#endif
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}
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/**
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* This function set interrupt pending flag.
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* @param vector: the interrupt number
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*/
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void rt_hw_interrupt_set_pending(int vector)
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{
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#ifdef BSP_USING_GIC
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arm_gic_set_pending_irq(0, vector);
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#endif
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}
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/**
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* This function get interrupt pending flag.
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* @param vector: the interrupt number
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* @return interrupt pending flag, 0: not pending; 1: pending
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*/
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unsigned int rt_hw_interrupt_get_pending(int vector)
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{
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#ifdef BSP_USING_GIC
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return arm_gic_get_pending_irq(0, vector);
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#else
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return -RT_ERROR;
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#endif
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}
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/**
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* This function clear interrupt pending flag.
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* @param vector: the interrupt number
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*/
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void rt_hw_interrupt_clear_pending(int vector)
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{
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#ifdef BSP_USING_GIC
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arm_gic_clear_pending_irq(0, vector);
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#endif
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}
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/**
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* This function set interrupt priority value.
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* @param vector: the interrupt number
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* priority: the priority of interrupt to set
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*/
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void rt_hw_interrupt_set_priority(int vector, unsigned int priority)
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{
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#ifdef BSP_USING_GIC
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arm_gic_set_priority(0, vector, priority);
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#endif
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}
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/**
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* This function get interrupt priority.
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* @param vector: the interrupt number
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* @return interrupt priority value
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*/
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unsigned int rt_hw_interrupt_get_priority(int vector)
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{
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#ifdef BSP_USING_GIC
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return arm_gic_get_priority(0, vector);
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#else
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return -RT_ERROR;
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#endif
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}
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/**
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* This function set priority masking threshold.
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* @param priority: priority masking threshold
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*/
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void rt_hw_interrupt_set_priority_mask(unsigned int priority)
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{
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#ifdef BSP_USING_GIC
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arm_gic_set_interface_prior_mask(0, priority);
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#endif
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}
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/**
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* This function get priority masking threshold.
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* @param none
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* @return priority masking threshold
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*/
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unsigned int rt_hw_interrupt_get_priority_mask(void)
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{
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#ifdef BSP_USING_GIC
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return arm_gic_get_interface_prior_mask(0);
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#else
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return -RT_ERROR;
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#endif
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}
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/**
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* This function set priority grouping field split point.
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* @param bits: priority grouping field split point
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* @return 0: success; -1: failed
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*/
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int rt_hw_interrupt_set_prior_group_bits(unsigned int bits)
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{
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#ifdef BSP_USING_GIC
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int status;
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if (bits < 8)
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{
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arm_gic_set_binary_point(0, (7 - bits));
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status = 0;
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}
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else
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{
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status = -1;
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}
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return (status);
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#else
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return -RT_ERROR;
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#endif
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}
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/**
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* This function get priority grouping field split point.
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* @param none
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* @return priority grouping field split point
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*/
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unsigned int rt_hw_interrupt_get_prior_group_bits(void)
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{
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#ifdef BSP_USING_GIC
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unsigned int bp;
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bp = arm_gic_get_binary_point(0) & 0x07;
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return (7 - bp);
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#else
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return -RT_ERROR;
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#endif
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector < MAX_HANDLERS)
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{
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old_handler = isr_table[vector].handler;
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if (handler != RT_NULL)
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{
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#ifdef RT_USING_INTERRUPT_INFO
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rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
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#endif /* RT_USING_INTERRUPT_INFO */
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isr_table[vector].handler = handler;
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isr_table[vector].param = param;
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}
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}
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return old_handler;
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}
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#ifdef RT_USING_SMP
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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#ifdef BSP_USING_GIC
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#ifdef BSP_USING_GICV2
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arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
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#else
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arm_gic_send_affinity_sgi(0, ipi_vector, (rt_uint64_t *)&cpu_mask, GICV3_ROUTED_TO_SPEC);
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#endif
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#else
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int i;
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__DSB();
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for (i = 0; i < RT_CPUS_NR; ++i)
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{
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if (cpu_mask & (1 << i))
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{
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IPI_MAILBOX_SET(i) = 1 << ipi_vector;
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}
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}
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__DSB();
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#endif
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}
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
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{
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/* note: ipi_vector maybe different with irq_vector */
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rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
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}
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#endif
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