rt-thread/libcpu/risc-v/virt64
Shell eec78d9f5d
[rt-smart] testcase & improvements for memory management (#7099)
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch
2023-03-30 08:25:15 +08:00
..
SConscript [atomic]添加arm与risc-v下的常用原子操作函数 (#7053) 2023-03-23 20:06:50 +08:00
backtrace.c [fixup] add cache maintenance ops; 2023-02-21 08:48:49 +08:00
cache.c [rt-smart] move sys_cacheflush to lwp_syscall.c (#7048) 2023-03-17 15:11:38 +08:00
cache.h [rt-smart] testcase & improvements for memory management (#7099) 2023-03-30 08:25:15 +08:00
context_gcc.S [rt-smart] kernel virtual memory management layer (#6809) 2023-01-08 21:08:55 -05:00
cpuport.c [smart][risc-v/libcpu] port rv64 cpu code (#6704) 2022-12-10 22:16:42 +08:00
cpuport.h [smart][risc-v/libcpu] port rv64 cpu code (#6704) 2022-12-10 22:16:42 +08:00
cpuport_gcc.S sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
encoding.h sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
ext_context.h sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
interrupt.c [smart][risc-v/libcpu] port rv64 cpu code (#6704) 2022-12-10 22:16:42 +08:00
interrupt.h [rt-smart] porting c906 and D1s to mm (#6848) 2023-01-16 08:24:03 +08:00
interrupt_gcc.S [smart][risc-v/libcpu] port rv64 cpu code (#6704) 2022-12-10 22:16:42 +08:00
io.h sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
mmu.c [fixup] add cache maintenance ops; 2023-02-21 08:48:49 +08:00
mmu.h [fixup] add cache maintenance ops; 2023-02-21 08:48:49 +08:00
plic.c [smart][risc-v/libcpu] port rv64 cpu code (#6704) 2022-12-10 22:16:42 +08:00
plic.h [smart][risc-v/libcpu] port rv64 cpu code (#6704) 2022-12-10 22:16:42 +08:00
riscv.h format code 2021-05-21 18:39:41 +08:00
riscv_io.h sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
riscv_mmu.c [rt-smart] kernel virtual memory management layer (#6809) 2023-01-08 21:08:55 -05:00
riscv_mmu.h [libcpu/risc-v] support noncached normal memory (#7051) 2023-03-16 10:26:55 +08:00
sbi.c [rt-smart] kernel virtual memory management layer (#6809) 2023-01-08 21:08:55 -05:00
sbi.h [rt-smart] kernel virtual memory management layer (#6809) 2023-01-08 21:08:55 -05:00
stack.h sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
stackframe.h [rt-smart] handling kernel from accessing unmapped user stack (#6957) 2023-02-24 14:52:16 +08:00
start.c [rt-smart] kernel virtual memory management layer (#6809) 2023-01-08 21:08:55 -05:00
startup_gcc.S [libcpu/riscv/virt64] fix (#5979) (#7040) 2023-03-11 12:34:14 +08:00
syscall_c.c [rt-smart] kernel virtual memory management layer (#6809) 2023-01-08 21:08:55 -05:00
tick.c sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
tick.h sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00
tlb.h [rt-smart] porting c906 and D1s to mm (#6848) 2023-01-16 08:24:03 +08:00
trap.c [rt-smart] testcase & improvements for memory management (#7099) 2023-03-30 08:25:15 +08:00
vector_encoding.h sync branch rt-smart. (#6641) 2022-12-03 12:07:44 +08:00