248 lines
7.1 KiB
C
Executable File
248 lines
7.1 KiB
C
Executable File
/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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/**
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* @addtogroup at91sam9260
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*/
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/*@{*/
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extern void rt_hw_clock_init(void);
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extern void rt_hw_mmu_init(void);
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extern void rt_hw_get_clock(void);
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extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
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extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
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/*set debug serial port*/
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//#define USE_UART1
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//#define USE_UART3
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#define USE_DBGU
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#define DBGU ((struct uartport *)0xfffff200)
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#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1)
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#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3)
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struct serial_int_rx uart0_int_rx;
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struct serial_device uart0 =
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{
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//UART0,
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DBGU,
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//UART1,
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//UART3,
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&uart0_int_rx,
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RT_NULL
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};
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struct rt_device uart0_device;
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/**
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* This function will handle serial
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*/
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void rt_serial_handler(int vector)
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{
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#ifdef USE_UART1
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int status;
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status = readl(AT91SAM9260_BASE_US1+AT91_US_CSR);
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if (!(status & readl(AT91SAM9260_BASE_US1+AT91_US_IMR)))
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{
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return;
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}
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#endif
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#ifdef USE_UART3
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at91_sys_read(AT91_USART3+AT91_US_CSR);
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#endif
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rt_hw_serial_isr(&uart0_device);
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}
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/**
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* This function will handle init uart
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*/
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void rt_hw_uart_init(void)
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{
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rt_uint32_t cd;
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#ifdef USE_UART1
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#define BAUDRATE 115200
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//rt_uint32_t uart_rate;
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//at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
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at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
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at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
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at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
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at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
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at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
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writel(AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS, AT91SAM9260_BASE_US1 + AT91_US_CR);
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writel( AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | AT91_US_CHRL_8 | AT91_US_PAR_NONE | AT91_US_NBSTOP_1 | AT91_US_CHMODE_NORMAL, AT91SAM9260_BASE_US1 + AT91_US_MR);//0x100108c0
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//at91_sys_write(AT91_USART1 + AT91_US_MR, 0x000008c0);//0x100108c0
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cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE;
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writel(cd, AT91SAM9260_BASE_US1 + AT91_US_BRGR);
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writel(AT91_US_RXEN | AT91_US_TXEN, AT91SAM9260_BASE_US1 + AT91_US_CR);
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writel(0x1, AT91SAM9260_BASE_US1 + AT91_US_IER);
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/* install interrupt handler */
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rt_hw_interrupt_install(AT91SAM9260_ID_US1, rt_serial_handler, RT_NULL);
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rt_hw_interrupt_umask(AT91SAM9260_ID_US1);
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#endif
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#ifdef USE_UART3
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#define BAUDRATE 115200
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//rt_uint32_t uart_rate;
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at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
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at91_sys_write(AT91_PIOB+0x04, (1<<10)|(1<<11));
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at91_sys_write(AT91_PIOB+0x70, (1<<10)|(1<<11));
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writel(AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS, AT91SAM9260_BASE_US1 + AT91_US_CR);
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writel( AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | AT91_US_CHRL_8 | AT91_US_PAR_NONE | AT91_US_NBSTOP_1 | AT91_US_CHMODE_NORMAL, AT91SAM9260_BASE_US3 + AT91_US_MR);
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cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE;
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writel(cd, AT91SAM9260_BASE_US3 + AT91_US_BRGR);
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writel(AT91_US_RXEN | AT91_US_TXEN, AT91SAM9260_BASE_US3 + AT91_US_CR);
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writel(0x1, AT91SAM9260_BASE_US3 + AT91_US_IER);
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/* install interrupt handler */
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rt_hw_interrupt_install(AT91SAM9260_ID_US3, rt_serial_handler, RT_NULL);
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rt_hw_interrupt_umask(AT91SAM9260_ID_US3);
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#endif
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#ifdef USE_DBGU
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#define BAUDRATE 115200
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//rt_uint32_t cd;
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at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
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//at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
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at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
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at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
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at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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at91_sys_write(AT91_DBGU + AT91_US_CR, AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS);
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at91_sys_write(AT91_DBGU + AT91_US_IDR, 0xffffffff);
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at91_sys_write(AT91_DBGU + AT91_US_MR, AT91_US_USMODE_NORMAL | AT91_US_PAR_NONE);
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cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE;
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at91_sys_write(AT91_DBGU + AT91_US_BRGR, cd);
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at91_sys_write(AT91_DBGU + AT91_US_CR, AT91_US_RXEN | AT91_US_TXEN);
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at91_sys_read(AT91_DBGU + AT91_US_CSR); //read for clearing interrupt
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at91_sys_write(AT91_DBGU + AT91_US_IER, 0x1);
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#endif
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}
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#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
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#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
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static rt_uint32_t pit_cycle; /* write-once */
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static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
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/**
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* This function will handle rtos timer
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*/
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void rt_timer_handler(int vector)
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{
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#ifdef USE_DBGU
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if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) {
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//rt_kprintf("DBGU interrupt occur\n");
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rt_serial_handler(1);
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}
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#endif
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if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) {
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unsigned nr_ticks;
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/* Get number of ticks performed before irq, and ack it */
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nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
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rt_tick_increase();
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}
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}
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static void at91sam926x_pit_reset(void)
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{
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/* Disable timer and irqs */
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at91_sys_write(AT91_PIT_MR, 0);
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/* Clear any pending interrupts, wait for PIT to stop counting */
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while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
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;
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/* Start PIT but don't enable IRQ */
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//at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
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pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
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at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
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| AT91_PIT_PITIEN);
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rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
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}
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/*
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* Set up both clocksource and clockevent support.
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*/
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static void at91sam926x_pit_init(void)
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{
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rt_uint32_t pit_rate;
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rt_uint32_t bits;
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/*
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* Use our actual MCK to figure out how many MCK/16 ticks per
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* 1/HZ period (instead of a compile-time constant LATCH).
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*/
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pit_rate = clk_get_rate(clk_get("mck")) / 16;
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rt_kprintf("pit_rate=%dHZ\n", pit_rate);
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pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
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/* Initialize and enable the timer */
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at91sam926x_pit_reset();
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}
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/**
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* This function will init pit for system ticks
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*/
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void rt_hw_timer_init()
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{
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at91sam926x_pit_init();
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/* install interrupt handler */
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rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, RT_NULL);
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rt_hw_interrupt_umask(AT91_ID_SYS);
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}
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void at91_tc1_init()
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{
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at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
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writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
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writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
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writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
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writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
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}
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/**
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* This function will init at91sam9260 board
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*/
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void rt_hw_board_init()
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{
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/* initialize the system clock */
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rt_hw_clock_init();
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/* initialize uart */
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rt_hw_uart_init();
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/* initialize mmu */
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//rt_hw_mmu_init();
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/* initialize timer0 */
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rt_hw_timer_init();
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}
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/*@}*/
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