409 lines
17 KiB
C
409 lines
17 KiB
C
/*
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* @brief SD/SDIO (MCI) registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __SDMMC_001_H_
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#define __SDMMC_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup IP_SDMMC_001 IP: SDMMC register block and driver
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* @ingroup IP_Drivers
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* @{
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*/
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/**
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* @brief SD/MMC & SDIO register block structure
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*/
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typedef struct { /*!< SDMMC Structure */
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__IO uint32_t CTRL; /*!< Control Register */
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__IO uint32_t PWREN; /*!< Power Enable Register */
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__IO uint32_t CLKDIV; /*!< Clock Divider Register */
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__IO uint32_t CLKSRC; /*!< SD Clock Source Register */
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__IO uint32_t CLKENA; /*!< Clock Enable Register */
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__IO uint32_t TMOUT; /*!< Timeout Register */
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__IO uint32_t CTYPE; /*!< Card Type Register */
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__IO uint32_t BLKSIZ; /*!< Block Size Register */
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__IO uint32_t BYTCNT; /*!< Byte Count Register */
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__IO uint32_t INTMASK; /*!< Interrupt Mask Register */
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__IO uint32_t CMDARG; /*!< Command Argument Register */
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__IO uint32_t CMD; /*!< Command Register */
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__I uint32_t RESP0; /*!< Response Register 0 */
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__I uint32_t RESP1; /*!< Response Register 1 */
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__I uint32_t RESP2; /*!< Response Register 2 */
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__I uint32_t RESP3; /*!< Response Register 3 */
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__I uint32_t MINTSTS; /*!< Masked Interrupt Status Register */
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__IO uint32_t RINTSTS; /*!< Raw Interrupt Status Register */
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__I uint32_t STATUS; /*!< Status Register */
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__IO uint32_t FIFOTH; /*!< FIFO Threshold Watermark Register */
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__I uint32_t CDETECT; /*!< Card Detect Register */
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__I uint32_t WRTPRT; /*!< Write Protect Register */
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__IO uint32_t GPIO; /*!< General Purpose Input/Output Register */
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__I uint32_t TCBCNT; /*!< Transferred CIU Card Byte Count Register */
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__I uint32_t TBBCNT; /*!< Transferred Host to BIU-FIFO Byte Count Register */
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__IO uint32_t DEBNCE; /*!< Debounce Count Register */
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__IO uint32_t USRID; /*!< User ID Register */
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__I uint32_t VERID; /*!< Version ID Register */
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__I uint32_t RESERVED0;
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__IO uint32_t UHS_REG; /*!< UHS-1 Register */
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__IO uint32_t RST_N; /*!< Hardware Reset */
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__I uint32_t RESERVED1;
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__IO uint32_t BMOD; /*!< Bus Mode Register */
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__O uint32_t PLDMND; /*!< Poll Demand Register */
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__IO uint32_t DBADDR; /*!< Descriptor List Base Address Register */
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__IO uint32_t IDSTS; /*!< Internal DMAC Status Register */
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__IO uint32_t IDINTEN; /*!< Internal DMAC Interrupt Enable Register */
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__I uint32_t DSCADDR; /*!< Current Host Descriptor Address Register */
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__I uint32_t BUFADDR; /*!< Current Buffer Descriptor Address Register */
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} IP_SDMMC_001_Type;
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/** @brief SDIO DMA descriptor control (des0) register defines
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*/
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#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */
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#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */
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#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */
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#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */
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#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */
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#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */
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#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */
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/** @brief SDIO DMA descriptor size (des1) register defines
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*/
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#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */
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#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */
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#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */
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/** @brief SDIO control register defines
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*/
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#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */
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#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */
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#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */
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#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */
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#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */
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#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */
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#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */
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#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */
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#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */
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#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */
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#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */
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#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */
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/** @brief SDIO Power Enable register defines
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*/
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#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */
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/** @brief SDIO Clock divider register defines
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*/
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#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */
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/** @brief SDIO Clock source register defines
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*/
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#define MCI_CLKSRC_CLKDIV0 0
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#define MCI_CLKSRC_CLKDIV1 1
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#define MCI_CLKSRC_CLKDIV2 2
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#define MCI_CLKSRC_CLKDIV3 3
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#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */
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/** @brief SDIO Clock Enable register defines
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*/
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#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */
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#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */
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/** @brief SDIO time-out register defines
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*/
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#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */
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#define MCI_TMOUT_DATA_MSK 0xFFFFFF00
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#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */
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#define MCI_TMOUT_RESP_MSK 0xFF
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/** @brief SDIO card-type register defines
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*/
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#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */
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#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */
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/** @brief SDIO Interrupt status & mask register defines
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*/
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#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */
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#define MCI_INT_EBE (1 << 15) /*!< End-bit error */
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#define MCI_INT_ACD (1 << 14) /*!< Auto command done */
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#define MCI_INT_SBE (1 << 13) /*!< Start bit error */
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#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */
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#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */
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#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */
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#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */
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#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */
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#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */
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#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */
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#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */
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#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */
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#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */
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#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */
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#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */
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#define MCI_INT_CD (1 << 0) /*!< Card detect */
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/** @brief SDIO Command register defines
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*/
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#define MCI_CMD_START (1UL << 31) /*!< Start command */
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#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */
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#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */
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#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */
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#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */
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#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */
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#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */
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#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */
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#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */
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#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */
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#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */
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#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */
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#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */
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#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */
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#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */
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#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */
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#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */
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#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */
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#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */
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#define MCI_CMD_INDX(n) ((n) & 0x1F)
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/** @brief SDIO status register definess
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*/
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#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
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/** @brief SDIO FIFO threshold defines
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*/
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#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
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#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
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#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
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#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
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#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
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#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
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#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
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#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
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#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
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#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
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/** @brief Bus mode register defines
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*/
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#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */
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#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */
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#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */
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#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */
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#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */
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#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */
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#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */
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#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */
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#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */
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#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */
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#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */
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#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */
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/** @brief Commonly used definitions
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*/
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#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */
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/** Function prototype for SD interface IRQ callback */
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typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
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/** Function prototype for SD detect and write protect status check */
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typedef int32_t (*PSCHECK_FUNC_T)(void);
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/** Function prototype for SD slot power enable or slot reset */
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typedef void (*PS_POWER_FUNC_T)(int32_t enable);
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/** @brief SDIO chained DMA descriptor
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*/
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typedef struct {
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volatile uint32_t des0; /*!< Control and status */
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volatile uint32_t des1; /*!< Buffer size(s) */
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volatile uint32_t des2; /*!< Buffer address pointer 1 */
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volatile uint32_t des3; /*!< Buffer address pointer 2 */
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} pSDMMC_DMA_Type;
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/** @brief SDIO device type
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*/
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typedef struct _sdif_device {
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// MCI_IRQ_CB_FUNC_T irq_cb;
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pSDMMC_DMA_Type mci_dma_dd[1 + (0x10000 / MCI_DMADES1_MAXTR)];
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// uint32_t sdio_clk_rate;
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// uint32_t sdif_slot_clk_rate;
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// int32_t clock_enabled;
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} sdif_device;
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/**
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* @brief Initializes the MCI card controller
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* @param pSDMMC Pointer to IP_SDMMC_001_Type structure
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* @return None
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*/
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void IP_SDMMC_Init(IP_SDMMC_001_Type *pSDMMC);
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/**
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* @brief Close the MCI
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @return None
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*/
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void IP_SDMMC_DeInit(IP_SDMMC_001_Type *pSDMMC);
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/**
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* @brief Set block size for transfer
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param bytes : block size in bytes
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* @return None
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*/
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void IP_SDMMC_SetBlkSize(IP_SDMMC_001_Type *pSDMMC, uint32_t bytes);
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/**
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* @brief Reset card in slot
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param reset : Sets SD_RST to passed state
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* @return None
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* Reset card in slot, must manually de-assert reset after assertion
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* (Uses SD_RST pin, set per reset parameter state)
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*/
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void IP_SDMMC_Reset(IP_SDMMC_001_Type *pSDMMC, int32_t reset);
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/**
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* @brief Enable or disable slot power
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param enable : !0 to enable, or 0 to disable
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* @return None
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* Enable or disable slot power, !0 = enable slot power
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* (Uses SD_POW pin, set to high or low based on enable parameter state)
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*/
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void IP_SDMMC_PowerOnOff(IP_SDMMC_001_Type *pSDMMC, int32_t enable);
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/**
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* @brief Detect if write protect is enabled
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @return Returns 1 if card is write protected, otherwise 0
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* Detect if write protect is enabled
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* (uses SD_WP pin, returns 1 if card is write protected)
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*/
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int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_Type *pSDMMC);
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/**
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* @brief Detect if an SD card is inserted
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @return Returns 0 if a card is detected, otherwise 1
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* Detect if an SD card is inserted
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* (uses SD_CD pin, returns 0 on card detect)
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*/
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int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_Type *pSDMMC);
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/**
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* @brief Function to send command to Card interface unit (CIU)
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param cmd : Command with all flags set
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* @param arg : Argument for the command
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* @return TRUE on times-out, otherwise FALSE
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*/
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int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_Type *pSDMMC, uint32_t cmd, uint32_t arg);
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/**
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* @brief Read the response from the last command
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param resp : Pointer to response array to fill
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* @return None
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*/
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void IP_SDMMC_GetResponse(IP_SDMMC_001_Type *pSDMMC, uint32_t *resp);
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/**
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* @brief Sets the SD bus clock speed
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param clk_rate : Input clock rate into the IP block
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* @param speed : Desired clock speed to the card
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* @return None
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*/
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void IP_SDMMC_SetClock(IP_SDMMC_001_Type *pSDMMC, uint32_t clk_rate, uint32_t speed);
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/**
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* @brief Function to set card type
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param ctype : card type
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* @return None
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*/
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void IP_SDMMC_SetCardType(IP_SDMMC_001_Type *pSDMMC, uint32_t ctype);
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/**
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* @brief Function to clear interrupt & FIFOs
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @return None
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*/
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void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_Type *pSDMMC);
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/**
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* @brief Returns the raw SD interface interrupt status
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @return Raw interrupt status of Or'ed values MCI_INT_*
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*/
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uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_Type *pSDMMC);
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/**
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* @brief Sets the raw SD interface interrupt status
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param iVal : Raw interrupts to set, Or'ed values MCI_INT_*
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* @return None
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*/
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void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal);
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/**
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* @brief Sets the SD interface interrupt mask
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param iVal : Interrupts to enable, Or'ed values MCI_INT_*
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* @return None
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*/
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void IP_SDMMC_SetIntMask(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal);
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/**
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* @brief Setup DMA descriptors
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* @param pSDMMC : Pointer to IP_SDMMC_001_Type structure
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* @param psdif_dev : SD interface device
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* @param addr : Address of buffer (source or destination)
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* @param size : size of buffer in bytes (64K max)
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* @return None
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*/
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void IP_SDMMC_DmaSetup(IP_SDMMC_001_Type *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size);
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/* Sets the transfer block size */
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void IP_SDMMC_SetBlockSize(IP_SDMMC_001_Type *pSDMMC, uint32_t blk_size);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SDMMC_001_H_ */
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