ecf2d82159
* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-10 RT-Thread the first version,
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* compatible to riscv-v-spec-1.0
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*/
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#ifndef __VECTOR_ENCODING_H__
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#define __VECTOR_ENCODING_H__
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/**
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* assembler names used for vset{i}vli vtypei immediate
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*/
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#define VEC_IMM_SEW_8 e8
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#define VEC_IMM_SEW_16 e16
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#define VEC_IMM_SEW_32 e32
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#define VEC_IMM_SEW_64 e64
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/* group setting, encoding by multiplier */
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#define VEC_IMM_LMUL_F8 mf8
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#define VEC_IMM_LMUL_F4 mf4
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#define VEC_IMM_LMUL_F2 mf2
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#define VEC_IMM_LMUL_1 m1
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#define VEC_IMM_LMUL_2 m2
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#define VEC_IMM_LMUL_4 m4
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#define VEC_IMM_LMUL_8 m8
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/* TAIL & MASK agnostic bits */
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#define VEC_IMM_TAIL_AGNOSTIC ta
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#define VEC_IMM_MASK_AGNOSTIC ma
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#define VEC_IMM_TAMA VEC_IMM_TAIL_AGNOSTIC, VEC_IMM_MASK_AGNOSTIC
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#define VEC_IMM_TAMU VEC_IMM_TAIL_AGNOSTIC
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#define VEC_IMM_TUMA VEC_IMM_MASK_AGNOSTIC
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/**
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* configuration setting instruction
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*/
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#define VEC_CONFIG_SETVLI(xVl, xAvl, vtype...) vsetvli xVl, xAvl, ##vtype
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#define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype
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#endif /* __VECTOR_ENCODING_H__ */ |