167 lines
4.7 KiB
C
167 lines
4.7 KiB
C
/*
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* File : cpuport.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-07-09 Bernard first version
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* 2010-09-11 Bernard add CPU reset implementation
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* 2015-07-06 chinesebear modified for loongson 1c
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*/
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#include <rtthread.h>
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#include "ls1c.h"
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register rt_uint32_t $GP __asm__ ("$28");
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/**
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* @addtogroup Loongson LS1B
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*/
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/*@{*/
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/**
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* this function will reset CPU
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*
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*/
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void rt_hw_cpu_reset(void)
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{
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/* open the watch-dog */
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WDT_EN = 0x01; /* watch dog enable */
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WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
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WDT_SET = 0x01; /* watch dog start */
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rt_kprintf("reboot system...\n");
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while (1);
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}
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/**
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* this function will shutdown CPU
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*
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*/
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void rt_hw_cpu_shutdown(void)
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{
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rt_kprintf("shutdown...\n");
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while (1);
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}
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extern rt_uint32_t cp0_get_cause(void);
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extern rt_uint32_t cp0_get_status(void);
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extern rt_uint32_t cp0_get_hi(void);
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extern rt_uint32_t cp0_get_lo(void);
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
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{
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rt_uint32_t *stk;
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static rt_uint32_t g_sr = 0;
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static rt_uint32_t g_gp = 0;
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if (g_sr == 0)
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{
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g_sr = cp0_get_status();
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g_sr &= 0xfffffffe;
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g_sr |= 0x8401;
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g_gp = $GP;
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}
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/** Start at stack top */
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stk = (rt_uint32_t *)stack_addr;
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*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
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*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
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*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
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*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
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*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
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*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
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*(--stk) = (rt_uint32_t) texit; /* ra */
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*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
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*(--stk) = (rt_uint32_t) stack_addr; /* sp */
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*(--stk) = (rt_uint32_t) g_gp; /* gp */
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*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
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*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
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*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
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*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
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*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
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*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
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*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
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*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
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*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
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*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
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*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
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*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
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*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
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*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
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*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
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*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
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*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
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*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
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*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
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*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
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*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
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*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
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*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
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*(--stk) = (rt_uint32_t) parameter; /* a0 */
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*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
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*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
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*(--stk) = (rt_uint32_t) 0x00000001; /* at */
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*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
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/* return task's current stack address */
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return (rt_uint8_t *)stk;
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}
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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#if defined(CONFIG_CPU_LOONGSON2)
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#define Hit_Invalidate_I 0x00
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#else
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#define Hit_Invalidate_I 0x10
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#endif
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#define Hit_Invalidate_D 0x11
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define Hit_Writeback_Inv_D 0x15
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void flush_cache(unsigned long start_addr, unsigned long size)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
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while (1) {
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cache_op(Hit_Writeback_Inv_D, addr);
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cache_op(Hit_Invalidate_I, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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/*@}*/
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