828 lines
41 KiB
PHP
828 lines
41 KiB
PHP
;/*****************************************************************************/
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;/* S3C2440.S: Startup file for Samsung S3C440 */
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;/*****************************************************************************/
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;/* <<< Use Configuration Wizard in Context Menu >>> */
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;/*****************************************************************************/
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;/* This file is part of the uVision/ARM development tools. */
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;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */
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;/* This software may only be used under the terms of a valid, current, */
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;/* end user licence from KEIL for a compatible version of KEIL software */
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;/* development tools. Nothing else gives you the right to use this software. */
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;/*****************************************************************************/
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;/*
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; * The S3C2440.S code is executed after CPU Reset. This file may be
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; * translated with the following SET symbols. In uVision these SET
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; * symbols are entered under Options - ASM - Define.
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; *
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; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock
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; * (used mostly when clock is already initialized from script .ini
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; * file).
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; *
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; * NO_MC_SETUP: when set the startup code will not initialize Memory
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; * Controller (used mostly when clock is already initialized from script
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; * .ini file).
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; *
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; * NO_GP_SETUP: when set the startup code will not initialize General Ports
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; * (used mostly when clock is already initialized from script .ini
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; * file).
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; *
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; * RAM_INTVEC: when set the startup code copies exception vectors
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; * from execution address to on-chip RAM.
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; */
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; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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;----------------------- Stack and Heap Definitions ----------------------------
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;// <h> Stack Configuration (Stack Sizes in Bytes)
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;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
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;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
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;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
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;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
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;// </h>
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UND_Stack_Size EQU 0x00000000
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SVC_Stack_Size EQU 0x00000100
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ABT_Stack_Size EQU 0x00000000
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FIQ_Stack_Size EQU 0x00000000
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IRQ_Stack_Size EQU 0x00000100
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USR_Stack_Size EQU 0x00000100
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ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE USR_Stack_Size
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__initial_sp SPACE ISR_Stack_Size
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Stack_Top
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;// <h> Heap Configuration
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;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
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;// </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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;----------------------- Memory Definitions ------------------------------------
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; Internal Memory Base Addresses
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IRAM_BASE EQU 0x40000000
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;----------------------- Watchdog Timer Definitions ----------------------------
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WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address
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WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset
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WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset
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WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset
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;// <e> Watchdog Timer Setup
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;// <h> Watchdog Timer Control Register (WTCON)
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;// <o1.8..15> Prescaler Value <0-255>
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;// <o1.5> Watchdog Timer Enable
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;// <o1.3..4> Clock Division Factor
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;// <0=> 16 <1=> 32 <2=> 64 <3=> 128
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;// <o1.2> Interrupt Generation Enable
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;// <o1.0> Reset Enable
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;// </h>
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;// <h> Watchdog Timer Data Register (WTDAT)
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;// <o2.0..15> Count Reload Value <0-65535>
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;// </h>
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;// </e> Watchdog Timer Setup
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WT_SETUP EQU 1
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WTCON_Val EQU 0x00000000
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WTDAT_Val EQU 0x00008000
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;----------------------- Clock and Power Management Definitions ----------------
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CLOCK_BASE EQU 0x4C000000 ; Clock Base Address
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LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset
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MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset
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UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset
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CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset
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CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset
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CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset
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CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset
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;// <e> Clock Setup
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;// <h> PLL Lock Time Count Register (LOCKTIME)
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;// <o1.16..31> U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF>
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;// <o1.0..15> M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF>
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;// </h>
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;// <h> MPLL Configuration Register (MPLLCON)
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;// <i> MPLL = (2 * m * Fin) / (p * 2^s)
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;// <o2.12..19> m: Main Divider m Value <9-256><#-8>
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;// <i> m = MDIV + 8
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;// <o2.4..9> p: Pre-divider p Value <3-64><#-2>
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;// <i> p = PDIV + 2
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;// <o2.0..1> s: Post Divider s Value <0-3>
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;// <i> s = SDIV
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;// </h>
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;// <h> UPLL Configuration Register (UPLLCON)
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;// <i> UPLL = ( m * Fin) / (p * 2^s)
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;// <o3.12..19> m: Main Divider m Value <8-263><#-8>
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;// <i> m = MDIV + 8
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;// <o3.4..9> p: Pre-divider p Value <2-65><#-2>
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;// <i> p = PDIV + 2
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;// <o3.0..1> s: Post Divider s Value <0-3>
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;// <i> s = SDIV
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;// </h>
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;// <h> Clock Generation Control Register (CLKCON)
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;// <o4.20> AC97 Enable
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;// <o4.19> Camera Enable
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;// <o4.18> SPI Enable
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;// <o4.17> IIS Enable
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;// <o4.16> IIC Enable
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;// <o4.15> ADC + Touch Screen Enable
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;// <o4.14> RTC Enable
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;// <o4.13> GPIO Enable
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;// <o4.12> UART2 Enable
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;// <o4.11> UART1 Enable
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;// <o4.10> UART0 Enable
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;// <o4.9> SDI Enable
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;// <o4.8> PWMTIMER Enable
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;// <o4.7> USB Device Enable
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;// <o4.6> USB Host Enable
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;// <o4.5> LCDC Enable
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;// <o4.4> NAND FLASH Controller Enable
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;// <o4.3> SLEEP Enable
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;// <o4.2> IDLE BIT Enable
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;// </h>
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;// <h> Clock Slow Control Register (CLKSLOW)
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;// <o5.7> UCLK_ON: UCLK ON
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;// <o5.5> MPLL_OFF: Turn off PLL
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;// <o5.4> SLOW_BIT: Slow Mode Enable
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;// <o5.0..2> SLOW_VAL: Slow Clock Divider <0-7>
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;// </h>
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;// <h> Clock Divider Control Register (CLKDIVN)
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;// <o6.3> DIVN_UPLL: UCLK Select
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;// <0=> UCLK = UPLL clock
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;// <1=> UCLK = UPLL clock / 2
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;// <o6.1..2> HDIVN: HCLK Select
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;// <0=> HCLK = FCLK
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;// <1=> HCLK = FCLK / 2
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;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8
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;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6
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;// <o6.0> PDIVN: PCLK Select
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;// <0=> PCLK = HCLK
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;// <1=> PCLK = HCLK / 2
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;// </h>
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;// <h> Camera Clock Divider Control Register (CAMDIVN)
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;// <o7.12> DVS_EN: ARM Core Clock Select
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;// <0=> ARM core runs at FCLK
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;// <1=> ARM core runs at HCLK
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;// <o7.9> HCLK4_HALF: HDIVN Division Rate Change Bit
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;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4
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;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8
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;// <o7.8> HCLK3_HALF: HDIVN Division Rate Change Bit
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;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3
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;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6
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;// <o7.4> CAMCLK Select
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;// <0=> CAMCLK = UPLL
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;// <1=> CAMCLK = UPLL / CAMCLK_DIV
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;// <o7.0..3> CAMCLK_DIV: CAMCLK Divider <0-15>
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;// <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1))
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;// <i> Divider is used only if CAMCLK_SEL = 1
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;// </h>
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;// </e> Clock Setup
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CLOCK_SETUP EQU 0
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LOCKTIME_Val EQU 0x0FFF0FFF
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MPLLCON_Val EQU 0x00043011
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UPLLCON_Val EQU 0x00038021
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CLKCON_Val EQU 0x001FFFF0
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CLKSLOW_Val EQU 0x00000004
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CLKDIVN_Val EQU 0x0000000F
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CAMDIVN_Val EQU 0x00000000
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;----------------------- Memory Controller Definitions -------------------------
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MC_BASE EQU 0x48000000 ; Memory Controller Base Address
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BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset
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BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset
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BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset
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BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset
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BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset
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BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset
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BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset
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BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset
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BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset
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REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset
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BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset
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MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset
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MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset
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;// <e> Memory Controller Setup
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;// <h> Bus Width and Wait Control Register (BWSCON)
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;// <o1.31> ST7: Use UB/LB for Bank 7
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;// <o1.30> WS7: Enable Wait Status for Bank 7
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;// <o1.28..29> DW7: Data Bus Width for Bank 7
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;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
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;// <o1.27> ST6: Use UB/LB for Bank 6
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;// <o1.26> WS6: Enable Wait Status for Bank 6
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;// <o1.24..25> DW6: Data Bus Width for Bank 6
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;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
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;// <o1.23> ST5: Use UB/LB for Bank 5
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;// <o1.22> WS5: Enable Wait Status for Bank 5
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;// <o1.20..21> DW5: Data Bus Width for Bank 5
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;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
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;// <o1.19> ST4: Use UB/LB for Bank 4
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;// <o1.18> WS4: Enable Wait Status for Bank 4
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;// <o1.16..17> DW4: Data Bus Width for Bank 4
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;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
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;// <o1.15> ST3: Use UB/LB for Bank 3
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;// <o1.14> WS3: Enable Wait Status for Bank 3
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;// <o1.12..13> DW3: Data Bus Width for Bank 3
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;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
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;// <o1.11> ST2: Use UB/LB for Bank 2
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;// <o1.10> WS2: Enable Wait Status for Bank 2
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;// <o1.8..9> DW2: Data Bus Width for Bank 2
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;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
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;// <o1.7> ST1: Use UB/LB for Bank 1
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;// <o1.6> WS1: Enable Wait Status for Bank 1
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;// <o1.4..5> DW1: Data Bus Width for Bank 1
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;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
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;// <o1.1..2> DW0: Indicate Data Bus Width for Bank 0
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;// <1=> 16-bit <2=> 32-bit
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;// </h>
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;// <h> Bank 0 Control Register (BANKCON0)
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;// <o2.13..14> Tacs: Address Set-up Time before nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o2.11..12> Tcos: Chip Selection Set-up Time before nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o2.8..10> Tacc: Access Cycle
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;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
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;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
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;// <o2.6..7> Tcoh: Chip Selection Hold Time after nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o2.4..5> Tcah: Address Hold Time after nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode
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;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
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;// <o2.0..1> PMC: Page Mode Configuration
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;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
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;// </h>
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;// <h> Bank 1 Control Register (BANKCON1)
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;// <o3.13..14> Tacs: Address Set-up Time before nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o3.11..12> Tcos: Chip Selection Set-up Time before nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o3.8..10> Tacc: Access Cycle
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;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
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;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
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;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o3.4..5> Tcah: Address Hold Time after nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode
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;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
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;// <o3.0..1> PMC: Page Mode Configuration
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;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
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;// </h>
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;// <h> Bank 2 Control Register (BANKCON2)
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;// <o4.13..14> Tacs: Address Set-up Time before nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o4.11..12> Tcos: Chip Selection Set-up Time before nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o4.8..10> Tacc: Access Cycle
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;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
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;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
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;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o4.4..5> Tcah: Address Hold Time after nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode
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;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
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;// <o4.0..1> PMC: Page Mode Configuration
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;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
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;// </h>
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;// <h> Bank 3 Control Register (BANKCON3)
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;// <o5.13..14> Tacs: Address Set-up Time before nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o5.11..12> Tcos: Chip Selection Set-up Time before nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o5.8..10> Tacc: Access Cycle
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;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
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;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
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;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o5.4..5> Tcah: Address Hold Time after nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode
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;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
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;// <o5.0..1> PMC: Page Mode Configuration
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;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
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;// </h>
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;// <h> Bank 4 Control Register (BANKCON4)
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;// <o6.13..14> Tacs: Address Set-up Time before nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o6.11..12> Tcos: Chip Selection Set-up Time before nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o6.8..10> Tacc: Access Cycle
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;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
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;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
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;// <o6.6..7> Tcoh: Chip Selection Hold Time after nOE
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o6.4..5> Tcah: Address Hold Time after nGCS
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
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;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode
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;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
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;// <o6.0..1> PMC: Page Mode Configuration
|
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;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
|
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;// </h>
|
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;// <h> Bank 5 Control Register (BANKCON5)
|
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;// <o7.13..14> Tacs: Address Set-up Time before nGCS
|
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
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;// <o7.11..12> Tcos: Chip Selection Set-up Time before nOE
|
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;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
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;// <o7.8..10> Tacc: Access Cycle
|
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;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
|
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;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
|
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;// <o7.6..7> Tcoh: Chip Selection Hold Time after nOE
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o7.4..5> Tcah: Address Hold Time after nGCS
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o7.2..3> Tacp: Page Mode Access Cycle at Page Mode
|
|
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
|
|
;// <o7.0..1> PMC: Page Mode Configuration
|
|
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
|
|
;// </h>
|
|
;// <h> Bank 6 Control Register (BANKCON6)
|
|
;// <o8.15..16> Memory Type Selection
|
|
;// <0=> ROM or SRAM <3=> SDRAM
|
|
;// <o8.13..14> Tacs: Address Set-up Time before nGCS
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o8.11..12> Tcos: Chip Selection Set-up Time before nOE
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o8.8..10> Tacc: Access Cycle
|
|
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
|
|
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
|
|
;// <o8.6..7> Tcoh: Chip Selection Hold Time after nOE
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o8.4..5> Tcah: Address Hold Time after nGCS
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o8.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
|
|
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
|
|
;// <i> if type is SDRAM then parameter is Trcd
|
|
;// <i> For SDRAM 6 cycles setting is not allowed
|
|
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
|
|
;// <o8.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
|
|
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
|
|
;// <i> if type is SDRAM then parameter is SCAN
|
|
;// </h>
|
|
;// <h> Bank 7 Control Register (BANKCON7)
|
|
;// <o9.15..16> Memory Type Selection
|
|
;// <0=> ROM or SRAM <3=> SDRAM
|
|
;// <o9.13..14> Tacs: Address Set-up Time before nGCS
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o9.11..12> Tcos: Chip Selection Set-up Time before nOE
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o9.8..10> Tacc: Access Cycle
|
|
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
|
|
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
|
|
;// <o9.6..7> Tcoh: Chip Selection Hold Time after nOE
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o9.4..5> Tcah: Address Hold Time after nGCS
|
|
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
|
|
;// <o9.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
|
|
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
|
|
;// <i> if type is SDRAM then parameter is Trcd
|
|
;// <i> For SDRAM 6 cycles setting is not allowed
|
|
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
|
|
;// <o9.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
|
|
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
|
|
;// <i> if type is SDRAM then parameter is SCAN
|
|
;// </h>
|
|
;// <h> SDRAM Refresh Control Register (REFRESH)
|
|
;// <o10.23> REFEN: SDRAM Refresh Enable
|
|
;// <o10.22> TREFMD: SDRAM Refresh Mode
|
|
;// <0=> CBR/Auto Refresh <1=> Self Refresh
|
|
;// <o10.20..21> Trp: SDRAM RAS Pre-charge Time
|
|
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved
|
|
;// <o10.18..19> Tsrc: SDRAM Semi Row Cycle Time
|
|
;// <i> SDRAM Row cycle time: Trc = Tsrc + Trp
|
|
;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
|
|
;// <o10.0..10> Refresh Counter <0-1023>
|
|
;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
|
|
;// </h>
|
|
;// <h> Flexible Bank Size Register (BANKSIZE)
|
|
;// <o11.7> BURST_EN: ARM Core Burst Operation Enable
|
|
;// <o11.5> SCKE_EN: SDRAM Power Down Mode Enable
|
|
;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle
|
|
;// <0=> SCLK is always active <1=> SCLK is active only during the access
|
|
;// <o11.0..2> BK76MAP: BANK6 and BANK7 Memory Map
|
|
;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB
|
|
;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB
|
|
;// <o11.0..10> Refresh Counter <0-1023>
|
|
;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
|
|
;// </h>
|
|
;// <h> SDRAM Mode Register Set Register 6 (MRSRB6)
|
|
;// <o12.7> WBL: Write Burst Length
|
|
;// <0=> Burst (Fixed)
|
|
;// <o12.7..8> TM: Test Mode
|
|
;// <0=> Mode register set (Fixed)
|
|
;// <o12.4..6> CL: CAS Latency
|
|
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
|
|
;// <o12.3> BT: Burst Type
|
|
;// <0=> Sequential (Fixed)
|
|
;// <o12.0..2> BL: Burst Length
|
|
;// <0=> 1 (Fixed)
|
|
;// </h>
|
|
;// <h> SDRAM Mode Register Set Register 7 (MRSRB7)
|
|
;// <o13.7> WBL: Write Burst Length
|
|
;// <0=> Burst (Fixed)
|
|
;// <o13.7..8> TM: Test Mode
|
|
;// <0=> Mode register set (Fixed)
|
|
;// <o13.4..6> CL: CAS Latency
|
|
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
|
|
;// <o13.3> BT: Burst Type
|
|
;// <0=> Sequential (Fixed)
|
|
;// <o13.0..2> BL: Burst Length
|
|
;// <0=> 1 (Fixed)
|
|
;// </h>
|
|
;// </e> Memory Controller Setup
|
|
MC_SETUP EQU 0
|
|
BWSCON_Val EQU 0x22000000
|
|
BANKCON0_Val EQU 0x00000700
|
|
BANKCON1_Val EQU 0x00000700
|
|
BANKCON2_Val EQU 0x00000700
|
|
BANKCON3_Val EQU 0x00000700
|
|
BANKCON4_Val EQU 0x00000700
|
|
BANKCON5_Val EQU 0x00000700
|
|
BANKCON6_Val EQU 0x00018005
|
|
BANKCON7_Val EQU 0x00018005
|
|
REFRESH_Val EQU 0x008404F3
|
|
BANKSIZE_Val EQU 0x00000032
|
|
MRSRB6_Val EQU 0x00000020
|
|
MRSRB7_Val EQU 0x00000020
|
|
|
|
|
|
;----------------------- I/O Port Definitions ----------------------------------
|
|
|
|
GPA_BASE EQU 0x56000000 ; GPA Base Address
|
|
GPB_BASE EQU 0x56000010 ; GPB Base Address
|
|
GPC_BASE EQU 0x56000020 ; GPC Base Address
|
|
GPD_BASE EQU 0x56000030 ; GPD Base Address
|
|
GPE_BASE EQU 0x56000040 ; GPE Base Address
|
|
GPF_BASE EQU 0x56000050 ; GPF Base Address
|
|
GPG_BASE EQU 0x56000060 ; GPG Base Address
|
|
GPH_BASE EQU 0x56000070 ; GPH Base Address
|
|
GPJ_BASE EQU 0x560000D0 ; GPJ Base Address
|
|
GPCON_OFS EQU 0x00 ; Control Register Offset
|
|
GPDAT_OFS EQU 0x04 ; Data Register Offset
|
|
GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset
|
|
|
|
;// <e> I/O Setup
|
|
GP_SETUP EQU 0
|
|
|
|
;// <e> Port A Settings
|
|
;// <h> Port A Control Register (GPACON)
|
|
;// <o1.22> GPA22 <0=> Output <1=> nFCE
|
|
;// <o1.21> GPA21 <0=> Output <1=> nRSTOUT
|
|
;// <o1.20> GPA20 <0=> Output <1=> nFRE
|
|
;// <o1.19> GPA19 <0=> Output <1=> nFWE
|
|
;// <o1.18> GPA18 <0=> Output <1=> ALE
|
|
;// <o1.17> GPA17 <0=> Output <1=> CLE
|
|
;// <o1.16> GPA16 <0=> Output <1=> nGCS[5]
|
|
;// <o1.15> GPA15 <0=> Output <1=> nGCS[4]
|
|
;// <o1.14> GPA14 <0=> Output <1=> nGCS[3]
|
|
;// <o1.13> GPA13 <0=> Output <1=> nGCS[2]
|
|
;// <o1.12> GPA12 <0=> Output <1=> nGCS[1]
|
|
;// <o1.11> GPA11 <0=> Output <1=> ADDR26
|
|
;// <o1.10> GPA10 <0=> Output <1=> ADDR25
|
|
;// <o1.9> GPA9 <0=> Output <1=> ADDR24
|
|
;// <o1.8> GPA8 <0=> Output <1=> ADDR23
|
|
;// <o1.7> GPA7 <0=> Output <1=> ADDR22
|
|
;// <o1.6> GPA6 <0=> Output <1=> ADDR21
|
|
;// <o1.5> GPA5 <0=> Output <1=> ADDR20
|
|
;// <o1.4> GPA4 <0=> Output <1=> ADDR19
|
|
;// <o1.3> GPA3 <0=> Output <1=> ADDR18
|
|
;// <o1.2> GPA2 <0=> Output <1=> ADDR17
|
|
;// <o1.1> GPA1 <0=> Output <1=> ADDR16
|
|
;// <o1.0> GPA0 <0=> Output <1=> ADDR0
|
|
;// </h>
|
|
;// </e>
|
|
GPA_SETUP EQU 0
|
|
GPACON_Val EQU 0x000003FF
|
|
|
|
;// <e> Port B Settings
|
|
;// <h> Port B Control Register (GPBCON)
|
|
;// <o1.20..21> GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved
|
|
;// <o1.18..19> GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved
|
|
;// <o1.16..17> GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved
|
|
;// <o1.14..15> GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved
|
|
;// <o1.12..13> GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved
|
|
;// <o1.10..11> GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved
|
|
;// <o1.8..9> GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved
|
|
;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved
|
|
;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved
|
|
;// <o1.2..3> GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved
|
|
;// <o1.0..1> GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
|
|
;// </h>
|
|
;// <h> Port B Pull-up Settings Register (GPBUP)
|
|
;// <o2.10> GPB10 Pull-up Disable
|
|
;// <o2.9> GPB9 Pull-up Disable
|
|
;// <o2.8> GPB8 Pull-up Disable
|
|
;// <o2.7> GPB7 Pull-up Disable
|
|
;// <o2.6> GPB6 Pull-up Disable
|
|
;// <o2.5> GPB5 Pull-up Disable
|
|
;// <o2.4> GPB4 Pull-up Disable
|
|
;// <o2.3> GPB3 Pull-up Disable
|
|
;// <o2.2> GPB2 Pull-up Disable
|
|
;// <o2.1> GPB1 Pull-up Disable
|
|
;// <o2.0> GPB0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPB_SETUP EQU 0
|
|
GPBCON_Val EQU 0x00000000
|
|
GPBUP_Val EQU 0x00000000
|
|
|
|
;// <e> Port C Settings
|
|
;// <h> Port C Control Register (GPCCON)
|
|
;// <o1.30..31> GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved
|
|
;// <o1.28..29> GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved
|
|
;// <o1.26..27> GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved
|
|
;// <o1.24..25> GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved
|
|
;// <o1.22..23> GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved
|
|
;// <o1.20..21> GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved
|
|
;// <o1.18..19> GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved
|
|
;// <o1.16..17> GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved
|
|
;// <o1.14..15> GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved
|
|
;// <o1.12..13> GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved
|
|
;// <o1.10..11> GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved
|
|
;// <o1.8..9> GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI
|
|
;// <o1.6..7> GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
|
|
;// <o1.4..5> GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
|
|
;// <o1.2..3> GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
|
|
;// <o1.0..1> GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved
|
|
;// </h>
|
|
;// <h> Port C Pull-up Settings Register (GPCUP)
|
|
;// <o2.15> GPC15 Pull-up Disable
|
|
;// <o2.14> GPC14 Pull-up Disable
|
|
;// <o2.13> GPC13 Pull-up Disable
|
|
;// <o2.12> GPC12 Pull-up Disable
|
|
;// <o2.11> GPC11 Pull-up Disable
|
|
;// <o2.10> GPC10 Pull-up Disable
|
|
;// <o2.9> GPC9 Pull-up Disable
|
|
;// <o2.8> GPC8 Pull-up Disable
|
|
;// <o2.7> GPC7 Pull-up Disable
|
|
;// <o2.6> GPC6 Pull-up Disable
|
|
;// <o2.5> GPC5 Pull-up Disable
|
|
;// <o2.4> GPC4 Pull-up Disable
|
|
;// <o2.3> GPC3 Pull-up Disable
|
|
;// <o2.2> GPC2 Pull-up Disable
|
|
;// <o2.1> GPC1 Pull-up Disable
|
|
;// <o2.0> GPC0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPC_SETUP EQU 0
|
|
GPCCON_Val EQU 0x00000000
|
|
GPCUP_Val EQU 0x00000000
|
|
|
|
;// <e> Port D Settings
|
|
;// <h> Port D Control Register (GPDCON)
|
|
;// <o1.30..31> GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0
|
|
;// <o1.28..29> GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1
|
|
;// <o1.26..27> GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved
|
|
;// <o1.24..25> GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved
|
|
;// <o1.22..23> GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved
|
|
;// <o1.20..21> GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1
|
|
;// <o1.18..19> GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1
|
|
;// <o1.16..17> GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1
|
|
;// <o1.14..15> GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved
|
|
;// <o1.12..13> GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved
|
|
;// <o1.10..11> GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved
|
|
;// <o1.8..9> GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved
|
|
;// <o1.6..7> GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved
|
|
;// <o1.4..5> GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved
|
|
;// <o1.2..3> GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved
|
|
;// <o1.0..1> GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved
|
|
;// </h>
|
|
;// <h> Port D Pull-up Settings Register (GPDUP)
|
|
;// <o2.15> GPD15 Pull-up Disable
|
|
;// <o2.14> GPD14 Pull-up Disable
|
|
;// <o2.13> GPD13 Pull-up Disable
|
|
;// <o2.12> GPD12 Pull-up Disable
|
|
;// <o2.11> GPD11 Pull-up Disable
|
|
;// <o2.10> GPD10 Pull-up Disable
|
|
;// <o2.9> GPD9 Pull-up Disable
|
|
;// <o2.8> GPD8 Pull-up Disable
|
|
;// <o2.7> GPD7 Pull-up Disable
|
|
;// <o2.6> GPD6 Pull-up Disable
|
|
;// <o2.5> GPD5 Pull-up Disable
|
|
;// <o2.4> GPD4 Pull-up Disable
|
|
;// <o2.3> GPD3 Pull-up Disable
|
|
;// <o2.2> GPD2 Pull-up Disable
|
|
;// <o2.1> GPD1 Pull-up Disable
|
|
;// <o2.0> GPD0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPD_SETUP EQU 0
|
|
GPDCON_Val EQU 0x00000000
|
|
GPDUP_Val EQU 0x00000000
|
|
|
|
;// <e> Port E Settings
|
|
;// <h> Port E Control Register (GPECON)
|
|
;// <o1.30..31> GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
|
|
;// <i> This pad is open-drain, and has no pull-up option.
|
|
;// <o1.28..29> GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
|
|
;// <i> This pad is open-drain, and has no pull-up option.
|
|
;// <o1.26..27> GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved
|
|
;// <o1.24..25> GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved
|
|
;// <o1.22..23> GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved
|
|
;// <o1.20..21> GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved
|
|
;// <o1.18..19> GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved
|
|
;// <o1.16..17> GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved
|
|
;// <o1.14..15> GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved
|
|
;// <o1.12..13> GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved
|
|
;// <o1.10..11> GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved
|
|
;// <o1.8..9> GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT
|
|
;// <o1.6..7> GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN
|
|
;// <o1.4..5> GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET
|
|
;// <o1.2..3> GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK
|
|
;// <o1.0..1> GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC
|
|
;// </h>
|
|
;// <h> Port E Pull-up Settings Register (GPEUP)
|
|
;// <o2.13> GPE13 Pull-up Disable
|
|
;// <o2.12> GPE12 Pull-up Disable
|
|
;// <o2.11> GPE11 Pull-up Disable
|
|
;// <o2.10> GPE10 Pull-up Disable
|
|
;// <o2.9> GPE9 Pull-up Disable
|
|
;// <o2.8> GPE8 Pull-up Disable
|
|
;// <o2.7> GPE7 Pull-up Disable
|
|
;// <o2.6> GPE6 Pull-up Disable
|
|
;// <o2.5> GPE5 Pull-up Disable
|
|
;// <o2.4> GPE4 Pull-up Disable
|
|
;// <o2.3> GPE3 Pull-up Disable
|
|
;// <o2.2> GPE2 Pull-up Disable
|
|
;// <o2.1> GPE1 Pull-up Disable
|
|
;// <o2.0> GPE0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPE_SETUP EQU 0
|
|
GPECON_Val EQU 0x00000000
|
|
GPEUP_Val EQU 0x00000000
|
|
|
|
;// <e> Port F Settings
|
|
;// <h> Port F Control Register (GPFCON)
|
|
;// <o1.14..15> GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved
|
|
;// <o1.12..13> GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved
|
|
;// <o1.10..11> GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved
|
|
;// <o1.8..9> GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved
|
|
;// <o1.6..7> GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved
|
|
;// <o1.4..5> GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved
|
|
;// <o1.2..3> GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved
|
|
;// <o1.0..1> GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved
|
|
;// </h>
|
|
;// <h> Port F Pull-up Settings Register (GPFUP)
|
|
;// <o2.7> GPF7 Pull-up Disable
|
|
;// <o2.6> GPF6 Pull-up Disable
|
|
;// <o2.5> GPF5 Pull-up Disable
|
|
;// <o2.4> GPF4 Pull-up Disable
|
|
;// <o2.3> GPF3 Pull-up Disable
|
|
;// <o2.2> GPF2 Pull-up Disable
|
|
;// <o2.1> GPF1 Pull-up Disable
|
|
;// <o2.0> GPF0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPF_SETUP EQU 0
|
|
GPFCON_Val EQU 0x00000000
|
|
GPFUP_Val EQU 0x00000000
|
|
|
|
;// <e> Port G Settings
|
|
;// <h> Port G Control Register (GPGCON)
|
|
;// <o1.30..31> GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved
|
|
;// <o1.28..29> GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved
|
|
;// <o1.26..27> GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved
|
|
;// <o1.24..25> GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved
|
|
;// <o1.22..23> GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1]
|
|
;// <o1.20..21> GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1
|
|
;// <o1.18..19> GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1
|
|
;// <o1.16..17> GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved
|
|
;// <o1.14..15> GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1
|
|
;// <o1.12..13> GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1
|
|
;// <o1.10..11> GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1
|
|
;// <o1.8..9> GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN
|
|
;// <o1.6..7> GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1
|
|
;// <o1.4..5> GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0
|
|
;// <o1.2..3> GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved
|
|
;// <o1.0..1> GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved
|
|
;// </h>
|
|
;// <h> Port G Pull-up Settings Register (GPGUP)
|
|
;// <o2.15> GPG15 Pull-up Disable
|
|
;// <o2.14> GPG14 Pull-up Disable
|
|
;// <o2.13> GPG13 Pull-up Disable
|
|
;// <o2.12> GPG12 Pull-up Disable
|
|
;// <o2.11> GPG11 Pull-up Disable
|
|
;// <o2.10> GPG10 Pull-up Disable
|
|
;// <o2.9> GPG9 Pull-up Disable
|
|
;// <o2.8> GPG8 Pull-up Disable
|
|
;// <o2.7> GPG7 Pull-up Disable
|
|
;// <o2.6> GPG6 Pull-up Disable
|
|
;// <o2.5> GPG5 Pull-up Disable
|
|
;// <o2.4> GPG4 Pull-up Disable
|
|
;// <o2.3> GPG3 Pull-up Disable
|
|
;// <o2.2> GPG2 Pull-up Disable
|
|
;// <o2.1> GPG1 Pull-up Disable
|
|
;// <o2.0> GPG0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPG_SETUP EQU 0
|
|
GPGCON_Val EQU 0x00000000
|
|
GPGUP_Val EQU 0x00000000
|
|
|
|
;// <e> Port H Settings
|
|
;// <h> Port H Control Register (GPHCON)
|
|
;// <o1.20..21> GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved
|
|
;// <o1.18..19> GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved
|
|
;// <o1.16..17> GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved
|
|
;// <o1.14..15> GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1
|
|
;// <o1.12..13> GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1
|
|
;// <o1.10..11> GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved
|
|
;// <o1.8..9> GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved
|
|
;// <o1.6..7> GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved
|
|
;// <o1.4..5> GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved
|
|
;// <o1.2..3> GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved
|
|
;// <o1.0..1> GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved
|
|
;// </h>
|
|
;// <h> Port H Pull-up Settings Register (GPHUP)
|
|
;// <o2.10> GPH10 Pull-up Disable
|
|
;// <o2.9> GPH9 Pull-up Disable
|
|
;// <o2.8> GPH8 Pull-up Disable
|
|
;// <o2.7> GPH7 Pull-up Disable
|
|
;// <o2.6> GPH6 Pull-up Disable
|
|
;// <o2.5> GPH5 Pull-up Disable
|
|
;// <o2.4> GPH4 Pull-up Disable
|
|
;// <o2.3> GPH3 Pull-up Disable
|
|
;// <o2.2> GPH2 Pull-up Disable
|
|
;// <o2.1> GPH1 Pull-up Disable
|
|
;// <o2.0> GPH0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPH_SETUP EQU 0
|
|
GPHCON_Val EQU 0x00000000
|
|
GPHUP_Val EQU 0x00000000
|
|
|
|
;// <e> Port J Settings
|
|
;// <h> Port J Control Register (GPJCON)
|
|
;// <o1.24..25> GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved
|
|
;// <o1.22..23> GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved
|
|
;// <o1.20..21> GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved
|
|
;// <o1.18..19> GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved
|
|
;// <o1.16..17> GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved
|
|
;// <o1.14..15> GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved
|
|
;// <o1.12..13> GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved
|
|
;// <o1.10..11> GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved
|
|
;// <o1.8..9> GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved
|
|
;// <o1.6..7> GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved
|
|
;// <o1.4..5> GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved
|
|
;// <o1.2..3> GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved
|
|
;// <o1.0..1> GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved
|
|
;// </h>
|
|
;// <h> Port J Pull-up Settings Register (GPJUP)
|
|
;// <o2.12> GPJ12 Pull-up Disable
|
|
;// <o2.11> GPJ11 Pull-up Disable
|
|
;// <o2.10> GPJ10 Pull-up Disable
|
|
;// <o2.9> GPJ9 Pull-up Disable
|
|
;// <o2.8> GPJ8 Pull-up Disable
|
|
;// <o2.7> GPJ7 Pull-up Disable
|
|
;// <o2.6> GPJ6 Pull-up Disable
|
|
;// <o2.5> GPJ5 Pull-up Disable
|
|
;// <o2.4> GPJ4 Pull-up Disable
|
|
;// <o2.3> GPJ3 Pull-up Disable
|
|
;// <o2.2> GPJ2 Pull-up Disable
|
|
;// <o2.1> GPJ1 Pull-up Disable
|
|
;// <o2.0> GPJ0 Pull-up Disable
|
|
;// </h>
|
|
;// </e>
|
|
GPJ_SETUP EQU 0
|
|
GPJCON_Val EQU 0x00000000
|
|
GPJUP_Val EQU 0x00000000
|
|
|
|
;// </e> I/O Setup
|
|
|
|
END |