293 lines
7.7 KiB
C
293 lines
7.7 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-1-16 Wayne First version
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*
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******************************************************************************/
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#include <rtdevice.h>
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#include <drv_gpio.h>
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#if defined(BOARD_USING_STORAGE_SPIFLASH)
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#if defined(RT_USING_SFUD)
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#include "spi_flash.h"
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#include "spi_flash_sfud.h"
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#endif
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#include "drv_qspi.h"
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#define W25X_REG_READSTATUS (0x05)
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#define W25X_REG_READSTATUS2 (0x35)
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#define W25X_REG_WRITEENABLE (0x06)
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#define W25X_REG_WRITESTATUS (0x01)
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#define W25X_REG_QUADENABLE (0x02)
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static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
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{
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rt_uint8_t u8Val;
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rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
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rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
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return u8Val;
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}
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static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
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{
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rt_uint8_t u8Val;
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rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
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rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
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return u8Val;
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}
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static void SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
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{
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rt_uint8_t w25x_txCMD1;
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rt_uint8_t u8Val[3];
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w25x_txCMD1 = W25X_REG_WRITEENABLE;
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rt_qspi_send(qspi_device, &w25x_txCMD1, 1);
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u8Val[0] = W25X_REG_WRITESTATUS;
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u8Val[1] = u8Value1;
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u8Val[2] = u8Value2;
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rt_qspi_send(qspi_device, &u8Val, 3);
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}
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static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
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{
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volatile uint8_t u8ReturnValue;
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do
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{
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u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
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u8ReturnValue = u8ReturnValue & 1;
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}
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while (u8ReturnValue != 0); // check the BUSY bit
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}
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static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
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{
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uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
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uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
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u8Status2 |= W25X_REG_QUADENABLE;
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SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
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SpiFlash_WaitReady(qspi_device);
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}
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static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
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{
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uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
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uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
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u8Status2 &= ~W25X_REG_QUADENABLE;
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SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
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SpiFlash_WaitReady(qspi_device);
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}
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static int rt_hw_spiflash_init(void)
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{
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/* Here, we use Dual I/O to drive the SPI flash by default. */
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/* If you want to use Quad I/O, you can modify to 4 from 2 and crossover D2/D3 pin of SPI flash. */
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if (nu_qspi_bus_attach_device("qspi0", "qspi01", 2, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
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return -1;
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#if defined(RT_USING_SFUD)
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if (rt_sfud_flash_probe("flash0", "qspi01") == RT_NULL)
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{
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return -(RT_ERROR);
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}
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#endif
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_spiflash_init);
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#endif /* BOARD_USING_STORAGE_SPIFLASH */
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#if defined(BOARD_USING_SRAM0_AS_MEMHEAP)
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/*
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In Advance board design, SRAM address bus A16/A17/A18 are GPIO-controlled by SW, not EBI.
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So we just remap 128KB only to RTT memory heap, due to it is out of controll.
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AD0~AD15: 2^16*16bit = 128KB
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*/
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#include <drv_ebi.h>
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#include "NuMicro.h"
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static struct rt_memheap system_heap;
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int nu_use_exsram_as_heap(void)
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{
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rt_err_t ret;
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/* Open ebi bank1 */
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ret = nu_ebi_init(EBI_BANK1, EBI_BUSWIDTH_16BIT, EBI_TIMING_SLOWEST, EBI_OPMODE_NORMAL, EBI_CS_ACTIVE_LOW);
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if (ret != RT_EOK)
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return ret;
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/* Initial sram as heap */
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return rt_memheap_init(&system_heap, "nu_sram_heap", (void *)EBI_BANK1_BASE_ADDR, 128 * 1024);
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}
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INIT_BOARD_EXPORT(nu_use_exsram_as_heap);
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#endif /* BOARD_USING_SRAM0_AS_MEMHEAP */
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#if defined(BOARD_USING_MAX31875)
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#include <sensor_max31875.h>
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int rt_hw_max31875_port(void)
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{
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struct rt_sensor_config cfg;
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cfg.intf.dev_name = "i2c1";
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cfg.intf.user_data = (void *)MAX31875_I2C_SLAVE_ADR_R0;
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cfg.irq_pin.pin = RT_PIN_NONE;
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rt_hw_max31875_init("max31875", &cfg);
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return 0;
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}
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INIT_APP_EXPORT(rt_hw_max31875_port);
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#endif /* BOARD_USING_MAX31875 */
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#if defined(BOARD_USING_MPU6500)
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#include <sensor_inven_mpu6xxx.h>
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int rt_hw_mpu6500_port(void)
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{
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struct rt_sensor_config cfg;
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cfg.intf.dev_name = "i2c2";
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cfg.intf.user_data = (void *)MPU6XXX_ADDR_DEFAULT;
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cfg.irq_pin.pin = RT_PIN_NONE;
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rt_hw_mpu6xxx_init("mpu", &cfg);
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return 0;
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}
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INIT_APP_EXPORT(rt_hw_mpu6500_port);
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#endif /* BOARD_USING_MPU6500 */
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#if defined(BOARD_USING_LCD_ILI9341) && defined(NU_PKG_USING_ILI9341_EBI)
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#include <lcd_ili9341.h>
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#if defined(PKG_USING_GUIENGINE)
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#include <rtgui/driver.h>
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#endif
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int rt_hw_ili9341_port(void)
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{
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rt_err_t ret = RT_EOK;
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/* Open ebi BOARD_USING_ILI9341_EBI_PORT */
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ret = nu_ebi_init(BOARD_USING_ILI9341_EBI_PORT, EBI_BUSWIDTH_16BIT, EBI_TIMING_NORMAL, EBI_OPMODE_NORMAL, EBI_CS_ACTIVE_LOW);
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if (ret != RT_EOK)
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return ret;
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switch (BOARD_USING_ILI9341_EBI_PORT)
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{
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case 0:
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EBI->CTL0 |= EBI_CTL0_CACCESS_Msk;
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EBI->TCTL0 |= (EBI_TCTL0_WAHDOFF_Msk | EBI_TCTL0_RAHDOFF_Msk);
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break;
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case 1:
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EBI->CTL1 |= EBI_CTL1_CACCESS_Msk;
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EBI->TCTL1 |= (EBI_TCTL1_WAHDOFF_Msk | EBI_TCTL1_RAHDOFF_Msk);
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break;
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case 2:
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EBI->CTL2 |= EBI_CTL2_CACCESS_Msk;
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EBI->TCTL2 |= (EBI_TCTL2_WAHDOFF_Msk | EBI_TCTL2_RAHDOFF_Msk);
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break;
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default:
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return -1;
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}
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if (rt_hw_lcd_ili9341_ebi_init(EBI_BANK0_BASE_ADDR + BOARD_USING_ILI9341_EBI_PORT * EBI_MAX_SIZE) != RT_EOK)
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return -1;
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rt_hw_lcd_ili9341_init();
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#if defined(PKG_USING_GUIENGINE)
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rt_device_t lcd_ili9341;
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lcd_ili9341 = rt_device_find("lcd");
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if (lcd_ili9341)
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{
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rtgui_graphic_set_device(lcd_ili9341);
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}
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#endif
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_ili9341_port);
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#endif /* BOARD_USING_LCD_ILI9341 */
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#if defined(BOARD_USING_NAU88L25) && defined(NU_PKG_USING_NAU88L25)
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#include <acodec_nau88l25.h>
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S_NU_NAU88L25_CONFIG sCodecConfig =
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{
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.i2c_bus_name = "i2c2",
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.i2s_bus_name = "sound0",
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.pin_phonejack_en = NU_GET_PININDEX(NU_PE, 13),
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.pin_phonejack_det = 0,
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};
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int rt_hw_nau88l25_port(void)
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{
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if (nu_hw_nau88l25_init(&sCodecConfig) != RT_EOK)
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return -1;
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return 0;
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}
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INIT_COMPONENT_EXPORT(rt_hw_nau88l25_port);
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#endif /* BOARD_USING_NAU88L25 */
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#if defined(BOARD_USING_BUZZER)
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#define BPWM_DEV_NAME "bpwm0"
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#define BPWM_DEV_CHANNEL (5)
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static void PlayRingTone(void)
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{
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struct rt_device_pwm *bpwm_dev;
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rt_uint32_t period;
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int i, j;
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period = 1000;
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if ((bpwm_dev = (struct rt_device_pwm *)rt_device_find(BPWM_DEV_NAME)) != RT_NULL)
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{
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rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period);
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rt_pwm_enable(bpwm_dev, BPWM_DEV_CHANNEL);
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for (j = 0; j < 5; j++)
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{
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for (i = 0; i < 10; i++)
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{
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rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period);
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rt_thread_mdelay(50);
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rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period/2);
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rt_thread_mdelay(50);
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}
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/* Mute 2 seconds */
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rt_pwm_set(bpwm_dev, BPWM_DEV_CHANNEL, period, period);
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rt_thread_mdelay(2000);
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}
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rt_pwm_disable(bpwm_dev, BPWM_DEV_CHANNEL);
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}
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else
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{
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rt_kprintf("Can't find %s\n", BPWM_DEV_NAME);
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}
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}
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int buzzer_test(void)
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{
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PlayRingTone();
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return 0;
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}
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#ifdef FINSH_USING_MSH
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MSH_CMD_EXPORT(buzzer_test, Buzzer - Play ring tone);
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#endif
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#endif /* BOARD_USING_BUZZER */
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