347 lines
8.7 KiB
C
347 lines
8.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-30 yangjie The first version for LPC54114
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "fsl_gpio.h"
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#include "LPC54114_cm4.h"
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#include "core_cm4.h"
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#include "fsl_inputmux.h"
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#include "fsl_pint.h"
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#include "fsl_iocon.h"
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#ifdef RT_USING_PIN
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#define get_port(x) (x / 32)
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#define get_pin(x) (x % 32)
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#define PIN_MAX_VAL 63
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#define IRQ_MAX_VAL 8
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static rt_base_t lpc_pin_get(const char *name)
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{
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rt_base_t pin = 0;
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int hw_port_num, hw_pin_num = 0;
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int i, name_len = 1;
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int mul = 1;
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name_len = rt_strlen(name);
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if ((name_len < 4) || (name_len >= 6))
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{
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return -RT_EINVAL;
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}
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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if ((name[1] >= '0') && (name[1] <= '9'))
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{
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hw_port_num = (int)(name[1] - '0');
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}
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else
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{
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return -RT_EINVAL;
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}
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for (i = name_len - 1; i > 2; i--)
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{
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hw_pin_num += ((int)(name[i] - '0') * mul);
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mul = mul * 10;
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}
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pin = 32 * hw_port_num + hw_pin_num;
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if ((pin > PIN_MAX_VAL) || (pin < 0))
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{
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return -RT_EINVAL;
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}
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return pin;
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}
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/* Configure pin mode. pin 0~63 means PIO0_0 ~ PIO1_31 */
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static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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int portx, piny, dir;
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uint32_t pin_cfg;
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if(pin > PIN_MAX_VAL)
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return;
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portx = get_port(pin);
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piny = get_pin(pin);
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switch(mode)
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{
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case PIN_MODE_OUTPUT:
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dir = kGPIO_DigitalOutput;
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pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN;
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break;
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case PIN_MODE_OUTPUT_OD:
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dir = kGPIO_DigitalOutput;
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pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN;
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break;
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case PIN_MODE_INPUT:
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dir = kGPIO_DigitalInput;
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pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN;
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break;
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case PIN_MODE_INPUT_PULLUP:
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dir = kGPIO_DigitalInput;
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pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP;
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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dir = kGPIO_DigitalInput;
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pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN;
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break;
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default: break;
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}
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CLOCK_EnableClock(kCLOCK_Iocon);
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IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
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GPIO_PortInit(GPIO, portx);
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gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 0};
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GPIO_PinInit(GPIO, portx, piny, &pin_config);
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CLOCK_DisableClock(kCLOCK_Iocon);
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}
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static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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int portx, piny;
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portx = get_port(pin);
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piny = get_pin(pin);
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if(pin > PIN_MAX_VAL)
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return;
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GPIO_PinWrite(GPIO, portx, piny, value);
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}
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static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int portx, piny, value;
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if(pin > PIN_MAX_VAL)
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return RT_ERROR;
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portx = get_port(pin);
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piny = get_pin(pin);
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value = (int)(GPIO_PinRead(GPIO, portx, piny));
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return value;
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}
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static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
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{
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int irqno = 0;
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for(irqno = 0; irqno < IRQ_MAX_VAL; irqno ++)
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{
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if((irqno) == pintr)
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{
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break;
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}
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}
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if(irqno >= IRQ_MAX_VAL)
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return;
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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void callback(pint_pin_int_t pintr, uint32_t pmatch_status)
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{
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pin_irq_hdr(pintr, pmatch_status);
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}
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static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i;
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if(pin > PIN_MAX_VAL)
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return RT_ERROR;
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portx = get_port(pin);
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piny = get_pin(pin);
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switch (mode)
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{
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case PIN_IRQ_MODE_RISING:
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trigger_mode = kPINT_PinIntEnableRiseEdge;
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break;
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case PIN_IRQ_MODE_FALLING:
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trigger_mode = kPINT_PinIntEnableFallEdge;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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trigger_mode = kPINT_PinIntEnableBothEdges;
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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trigger_mode = kPINT_PinIntEnableHighLevel;
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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trigger_mode = kPINT_PinIntEnableLowLevel;
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break;
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}
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/* Get inputmux_connection_t */
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pintsel = (pin + (0xC0U << 20));
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for(i = 0; i < IRQ_MAX_VAL; i++)
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{
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if(pin_irq_hdr_tab[i].pin == -1)
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{
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pin_initx = kPINT_PinInt0 + i;
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pin_irq_hdr_tab[i].pin = pin;
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pin_irq_hdr_tab[i].mode = trigger_mode;
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pin_irq_hdr_tab[i].hdr = hdr;
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pin_irq_hdr_tab[i].args = args;
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break;
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}
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}
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if(i >= IRQ_MAX_VAL)
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return RT_ERROR;
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/* open clk */
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CLOCK_EnableClock(kCLOCK_InputMux);
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CLOCK_EnableClock(kCLOCK_Iocon);
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/* AttachSignal */
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INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel);
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pin_cfg = ((IOCON->PIO[portx][piny] &
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(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */
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| IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */
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| IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */
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| IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */
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IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
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/* PINT_PinInterruptConfig */
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PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);
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CLOCK_DisableClock(kCLOCK_InputMux);
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CLOCK_DisableClock(kCLOCK_Iocon);
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return RT_EOK;
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}
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static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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int i;
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if(pin > PIN_MAX_VAL)
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return RT_ERROR;
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for(i = 0; i < IRQ_MAX_VAL; i++)
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{
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if(pin_irq_hdr_tab[i].pin == pin)
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{
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pin_irq_hdr_tab[i].pin = -1;
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pin_irq_hdr_tab[i].hdr = RT_NULL;
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pin_irq_hdr_tab[i].mode = 0;
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pin_irq_hdr_tab[i].args = RT_NULL;
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break;
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}
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}
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return RT_EOK;
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}
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static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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int irqn_type, i;
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if(pin > PIN_MAX_VAL)
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return RT_ERROR;
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for(i = 0; i < IRQ_MAX_VAL; i++)
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{
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if(pin_irq_hdr_tab[i].pin == pin)
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{
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switch(i)
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{
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case 0: irqn_type = PIN_INT0_IRQn; break;
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case 1: irqn_type = PIN_INT1_IRQn; break;
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case 2: irqn_type = PIN_INT2_IRQn; break;
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case 3: irqn_type = PIN_INT3_IRQn; break;
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case 4: irqn_type = PIN_INT4_IRQn; break;
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case 5: irqn_type = PIN_INT5_IRQn; break;
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case 6: irqn_type = PIN_INT6_IRQn; break;
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case 7: irqn_type = PIN_INT7_IRQn; break;
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default:break;
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}
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if(enabled)
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{
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/* PINT_EnableCallback */
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PINT_PinInterruptClrStatusAll(PINT);
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NVIC_ClearPendingIRQ((IRQn_Type)irqn_type);
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PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i));
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EnableIRQ((IRQn_Type)irqn_type);
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}
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else
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{
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/* PINT_DisableCallback */
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DisableIRQ((IRQn_Type)irqn_type);
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PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i));
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NVIC_ClearPendingIRQ((IRQn_Type)irqn_type);
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}
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break;
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}
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}
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if(i >= IRQ_MAX_VAL)
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return RT_ERROR;
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return RT_EOK;
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}
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const static struct rt_pin_ops _lpc_pin_ops =
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{
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lpc_pin_mode,
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lpc_pin_write,
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lpc_pin_read,
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lpc_pin_attach_irq,
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lpc_pin_detach_irq,
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lpc_pin_irq_enable,
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lpc_pin_get,
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};
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int rt_hw_pin_init(void)
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{
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int result;
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PINT_Init(PINT);
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result = rt_device_pin_register("pin", &_lpc_pin_ops, RT_NULL);
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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#endif
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