141 lines
3.5 KiB
ArmAsm
141 lines
3.5 KiB
ArmAsm
/*
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* File : cp15_gcc.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2013, RT-Thread Development Team
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* http://www.rt-thread.org
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-05 Bernard the first version
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*/
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.globl rt_cpu_get_smp_id
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rt_cpu_get_smp_id:
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mrc p15, #0, r0, c0, c0, #5
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bx lr
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.globl rt_cpu_vector_set_base
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rt_cpu_vector_set_base:
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mcr p15, #0, r0, c12, c0, #0
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dsb
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bx lr
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.globl rt_hw_cpu_dcache_enable
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rt_hw_cpu_dcache_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x00000004
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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.globl rt_hw_cpu_icache_enable
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rt_hw_cpu_icache_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x00001000
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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_FLD_MAX_WAY:
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.word 0x3ff
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_FLD_MAX_IDX:
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.word 0x7ff
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.globl rt_cpu_dcache_clean_flush
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rt_cpu_dcache_clean_flush:
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push {r4-r11}
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dmb
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mrc p15, #1, r0, c0, c0, #1 @ read clid register
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ands r3, r0, #0x7000000 @ get level of coherency
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mov r3, r3, lsr #23
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beq finished
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mov r10, #0
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loop1:
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add r2, r10, r10, lsr #1
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mov r1, r0, lsr r2
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and r1, r1, #7
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cmp r1, #2
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blt skip
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mcr p15, #2, r10, c0, c0, #0
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isb
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mrc p15, #1, r1, c0, c0, #0
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and r2, r1, #7
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add r2, r2, #4
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ldr r4, _FLD_MAX_WAY
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ands r4, r4, r1, lsr #3
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clz r5, r4
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ldr r7, _FLD_MAX_IDX
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ands r7, r7, r1, lsr #13
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loop2:
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mov r9, r4
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loop3:
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orr r11, r10, r9, lsl r5
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orr r11, r11, r7, lsl r2
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mcr p15, #0, r11, c7, c14, #2
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subs r9, r9, #1
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bge loop3
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subs r7, r7, #1
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bge loop2
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skip:
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add r10, r10, #2
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cmp r3, r10
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bgt loop1
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finished:
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dsb
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isb
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pop {r4-r11}
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bx lr
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.globl rt_hw_cpu_dcache_disable
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rt_hw_cpu_dcache_disable:
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push {r4-r11, lr}
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bl rt_cpu_dcache_clean_flush
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #0x00000004
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mcr p15, #0, r0, c1, c0, #0
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pop {r4-r11, lr}
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bx lr
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.globl rt_hw_cpu_icache_disable
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rt_hw_cpu_icache_disable:
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #0x00001000
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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.globl rt_cpu_mmu_disable
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rt_cpu_mmu_disable:
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mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #1
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mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
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dsb
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bx lr
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.globl rt_cpu_mmu_enable
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rt_cpu_mmu_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x001
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mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
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dsb
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bx lr
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.globl rt_cpu_tlb_set
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rt_cpu_tlb_set:
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mcr p15, #0, r0, c2, c0, #0
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dmb
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bx lr
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