798 lines
27 KiB
C
798 lines
27 KiB
C
/*!
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\file gd32e230_i2c.c
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\brief I2C driver
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\version 2018-06-19, V1.0.0, firmware for GD32E230
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32e230_i2c.h"
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/* I2C register bit mask */
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#define I2CCLK_MAX ((uint32_t)0x0000007FU) /*!< i2cclk maximum value */
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#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */
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#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */
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#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */
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#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */
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/* I2C register bit offset */
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#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */
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/*!
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\brief reset I2C
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[out] none
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\retval none
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*/
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void i2c_deinit(uint32_t i2c_periph)
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{
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switch(i2c_periph){
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case I2C0:
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/* reset I2C0 */
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rcu_periph_reset_enable(RCU_I2C0RST);
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rcu_periph_reset_disable(RCU_I2C0RST);
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break;
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case I2C1:
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/* reset I2C1 */
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rcu_periph_reset_enable(RCU_I2C1RST);
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rcu_periph_reset_disable(RCU_I2C1RST);
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break;
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default:
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break;
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}
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}
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/*!
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\brief configure I2C clock
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
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and fast mode plus (up to 1MHz)
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\param[in] dutycyc: duty cycle in fast mode or fast mode plus
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only one parameter can be selected which is shown as below:
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\arg I2C_DTCY_2: T_low/T_high=2
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\arg I2C_DTCY_16_9: T_low/T_high=16/9
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\param[out] none
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\retval none
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*/
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void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
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{
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uint32_t pclk1, clkc, freq, risetime;
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uint32_t temp;
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pclk1 = rcu_clock_freq_get(CK_APB1);
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/* I2C peripheral clock frequency */
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freq = (uint32_t)(pclk1/1000000U);
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if(freq >= I2CCLK_MAX){
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freq = I2CCLK_MAX;
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}
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temp = I2C_CTL1(i2c_periph);
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temp &= ~I2C_CTL1_I2CCLK;
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temp |= freq;
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I2C_CTL1(i2c_periph) = temp;
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if(100000U >= clkspeed){
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/* the maximum SCL rise time is 1000ns in standard mode */
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risetime = (uint32_t)((pclk1/1000000U)+1U);
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if(risetime >= I2CCLK_MAX){
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I2C_RT(i2c_periph) = I2CCLK_MAX;
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}else if(risetime <= I2CCLK_MIN){
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I2C_RT(i2c_periph) = I2CCLK_MIN;
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}else{
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I2C_RT(i2c_periph) = risetime;
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}
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clkc = (uint32_t)(pclk1/(clkspeed*2U));
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if(clkc < 0x04U){
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/* the CLKC in standard mode minmum value is 4 */
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clkc = 0x04U;
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}
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I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc);
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}else if(400000U >= clkspeed){
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/* the maximum SCL rise time is 300ns in fast mode */
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I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U);
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if(I2C_DTCY_2 == dutycyc){
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/* I2C duty cycle is 2 */
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clkc = (uint32_t)(pclk1/(clkspeed*3U));
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I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
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}else{
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/* I2C duty cycle is 16/9 */
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clkc = (uint32_t)(pclk1/(clkspeed*25U));
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I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
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}
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if(0U == (clkc & I2C_CKCFG_CLKC)){
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/* the CLKC in fast mode minmum value is 1 */
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clkc |= 0x0001U;
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}
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I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
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I2C_CKCFG(i2c_periph) |= clkc;
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}else{
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/* fast mode plus, the maximum SCL rise time is 120ns */
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I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U);
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if(I2C_DTCY_2 == dutycyc){
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/* I2C duty cycle is 2 */
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clkc = (uint32_t)(pclk1/(clkspeed*3U));
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I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
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}else{
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/* I2C duty cycle is 16/9 */
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clkc = (uint32_t)(pclk1/(clkspeed*25U));
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I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
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}
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/* enable fast mode */
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I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
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I2C_CKCFG(i2c_periph) |= clkc;
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/* enable I2C fast mode plus */
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I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN;
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}
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}
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/*!
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\brief configure I2C address
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] mode:
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only one parameter can be selected which is shown as below:
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\arg I2C_I2CMODE_ENABLE: I2C mode
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\arg I2C_SMBUSMODE_ENABLE: SMBus mode
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\param[in] addformat: 7bits or 10bits
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only one parameter can be selected which is shown as below:
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\arg I2C_ADDFORMAT_7BITS: 7bits
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\arg I2C_ADDFORMAT_10BITS: 10bits
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\param[in] addr: I2C address
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\param[out] none
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\retval none
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*/
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void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr)
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{
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/* SMBus/I2C mode selected */
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uint32_t ctl = 0U;
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ctl = I2C_CTL0(i2c_periph);
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ctl &= ~(I2C_CTL0_SMBEN);
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ctl |= mode;
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I2C_CTL0(i2c_periph) = ctl;
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/* configure address */
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addr = addr & I2C_ADDRESS_MASK;
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I2C_SADDR0(i2c_periph) = (addformat | addr);
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}
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/*!
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\brief SMBus type selection
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] type:
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only one parameter can be selected which is shown as below:
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\arg I2C_SMBUS_DEVICE: device
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\arg I2C_SMBUS_HOST: host
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\param[out] none
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\retval none
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*/
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void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
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{
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if(I2C_SMBUS_HOST == type){
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I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL;
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}else{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL);
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}
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}
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/*!
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\brief whether or not to send an ACK
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] ack:
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only one parameter can be selected which is shown as below:
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\arg I2C_ACK_ENABLE: ACK will be sent
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\arg I2C_ACK_DISABLE: ACK will not be sent
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\param[out] none
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\retval none
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*/
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void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
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{
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if(I2C_ACK_ENABLE == ack){
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I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
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}else{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
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}
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}
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/*!
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\brief configure I2C POAP position
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] pos:
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only one parameter can be selected which is shown as below:
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\arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
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\arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
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\param[out] none
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\retval none
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*/
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void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
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{
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/* configure I2C POAP position */
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if(I2C_ACKPOS_NEXT == pos){
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I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
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}else{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
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}
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}
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/*!
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\brief master sends slave address
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] addr: slave address
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\param[in] trandirection: transmitter or receiver
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only one parameter can be selected which is shown as below:
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\arg I2C_TRANSMITTER: transmitter
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\arg I2C_RECEIVER: receiver
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\param[out] none
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\retval none
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*/
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void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection)
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{
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/* master is a transmitter or a receiver */
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if(I2C_TRANSMITTER == trandirection){
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addr = addr & I2C_TRANSMITTER;
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}else{
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addr = addr | I2C_RECEIVER;
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}
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/* send slave address */
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I2C_DATA(i2c_periph) = addr;
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}
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/*!
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\brief enable dual-address mode
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] addr: the second address in dual-address mode
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\param[out] none
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\retval none
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*/
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void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr)
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{
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/* configure address */
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addr = addr & I2C_ADDRESS2_MASK;
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I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr);
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}
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/*!
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\brief disable dual-address mode
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[out] none
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\retval none
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*/
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void i2c_dualaddr_disable(uint32_t i2c_periph)
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{
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I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN);
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}
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/*!
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\brief enable I2C
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[out] none
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\retval none
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*/
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void i2c_enable(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN;
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}
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/*!
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\brief disable I2C
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[out] none
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\retval none
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*/
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void i2c_disable(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN);
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}
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/*!
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\brief generate a START condition on I2C bus
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[out] none
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\retval none
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*/
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void i2c_start_on_bus(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) |= I2C_CTL0_START;
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}
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/*!
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\brief generate a STOP condition on I2C bus
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[out] none
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\retval none
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*/
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void i2c_stop_on_bus(uint32_t i2c_periph)
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{
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I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP;
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}
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/*!
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\brief I2C transmit data function
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] data: data of transmission
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\param[out] none
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\retval none
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*/
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void i2c_data_transmit(uint32_t i2c_periph, uint8_t data)
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{
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I2C_DATA(i2c_periph) = DATA_TRANS(data);
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}
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/*!
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\brief I2C receive data function
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[out] none
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\retval data of received
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*/
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uint8_t i2c_data_receive(uint32_t i2c_periph)
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{
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return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph));
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}
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/*!
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\brief enable I2C DMA mode
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] dmastate:
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only one parameter can be selected which is shown as below:
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\arg I2C_DMA_ON: DMA mode enable
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\arg I2C_DMA_OFF: DMA mode disable
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\param[out] none
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\retval none
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*/
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void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
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{
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/* configure I2C DMA function */
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uint32_t ctl = 0U;
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ctl = I2C_CTL1(i2c_periph);
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ctl &= ~(I2C_CTL1_DMAON);
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ctl |= dmastate;
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I2C_CTL1(i2c_periph) = ctl;
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}
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/*!
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\brief configure whether next DMA EOT is DMA last transfer or not
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] dmalast:
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only one parameter can be selected which is shown as below:
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\arg I2C_DMALST_ON: next DMA EOT is the last transfer
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\arg I2C_DMALST_OFF: next DMA EOT is not the last transfer
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\param[out] none
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\retval none
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*/
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void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast)
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{
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/* configure DMA last transfer */
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uint32_t ctl = 0U;
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ctl = I2C_CTL1(i2c_periph);
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ctl &= ~(I2C_CTL1_DMALST);
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ctl |= dmalast;
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I2C_CTL1(i2c_periph) = ctl;
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}
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/*!
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\brief whether to stretch SCL low when data is not ready in slave mode
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] stretchpara:
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only one parameter can be selected which is shown as below:
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\arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
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\arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
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\param[out] none
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\retval none
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*/
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void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
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{
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/* configure I2C SCL strerching enable or disable */
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uint32_t ctl = 0U;
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ctl = I2C_CTL0(i2c_periph);
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ctl &= ~(I2C_CTL0_SS);
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ctl |= stretchpara;
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I2C_CTL0(i2c_periph) = ctl;
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}
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/*!
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\brief whether or not to response to a general call
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] gcallpara:
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only one parameter can be selected which is shown as below:
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\arg I2C_GCEN_ENABLE: slave will response to a general call
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\arg I2C_GCEN_DISABLE: slave will not response to a general call
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\param[out] none
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\retval none
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*/
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void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
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{
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/* configure slave response to a general call enable or disable */
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uint32_t ctl = 0U;
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ctl = I2C_CTL0(i2c_periph);
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ctl &= ~(I2C_CTL0_GCEN);
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ctl |= gcallpara;
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I2C_CTL0(i2c_periph) = ctl;
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}
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/*!
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\brief software reset I2C
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\param[in] i2c_periph: I2Cx(x=0,1)
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\param[in] sreset:
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only one parameter can be selected which is shown as below:
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\arg I2C_SRESET_SET: I2C is under reset
|
|
\arg I2C_SRESET_RESET: I2C is not under reset
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
|
|
{
|
|
/* modify CTL0 and configure software reset I2C state */
|
|
uint32_t ctl = 0U;
|
|
|
|
ctl = I2C_CTL0(i2c_periph);
|
|
ctl &= ~(I2C_CTL0_SRESET);
|
|
ctl |= sreset;
|
|
I2C_CTL0(i2c_periph) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief I2C PEC calculation on or off
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] pecpara:
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_PEC_ENABLE: PEC calculation on
|
|
\arg I2C_PEC_DISABLE: PEC calculation off
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
|
|
{
|
|
/* on/off PEC calculation */
|
|
uint32_t ctl = 0U;
|
|
|
|
ctl = I2C_CTL0(i2c_periph);
|
|
ctl &= ~(I2C_CTL0_PECEN);
|
|
ctl |= pecstate;
|
|
I2C_CTL0(i2c_periph) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief I2C whether to transfer PEC value
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] pecpara:
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_PECTRANS_ENABLE: transfer PEC
|
|
\arg I2C_PECTRANS_DISABLE: not transfer PEC
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
|
|
{
|
|
/* whether to transfer PEC */
|
|
uint32_t ctl = 0U;
|
|
|
|
ctl = I2C_CTL0(i2c_periph);
|
|
ctl &= ~(I2C_CTL0_PECTRANS);
|
|
ctl |= pecpara;
|
|
I2C_CTL0(i2c_periph) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief get packet error checking value
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[out] none
|
|
\retval PEC value
|
|
*/
|
|
uint8_t i2c_pec_value_get(uint32_t i2c_periph)
|
|
{
|
|
return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET);
|
|
}
|
|
|
|
/*!
|
|
\brief I2C issue alert through SMBA pin
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] smbuspara:
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin
|
|
\arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
|
|
{
|
|
/* issue alert through SMBA pin configure*/
|
|
uint32_t ctl = 0U;
|
|
|
|
ctl = I2C_CTL0(i2c_periph);
|
|
ctl &= ~(I2C_CTL0_SALT);
|
|
ctl |= smbuspara;
|
|
I2C_CTL0(i2c_periph) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief enable or disable I2C ARP protocol in SMBus switch
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] smbuspara:
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_ARP_ENABLE: enable ARP
|
|
\arg I2C_ARP_DISABLE: disable ARP
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
|
|
{
|
|
/* enable or disable I2C ARP protocol*/
|
|
uint32_t ctl = 0U;
|
|
|
|
ctl = I2C_CTL0(i2c_periph);
|
|
ctl &= ~(I2C_CTL0_ARPEN);
|
|
ctl |= arpstate;
|
|
I2C_CTL0(i2c_periph) = ctl;
|
|
}
|
|
|
|
/*!
|
|
\brief enable SAM_V interface
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_sam_enable(uint32_t i2c_periph)
|
|
{
|
|
I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN;
|
|
}
|
|
|
|
/*!
|
|
\brief disable SAM_V interface
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_sam_disable(uint32_t i2c_periph)
|
|
{
|
|
I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN);
|
|
}
|
|
|
|
/*!
|
|
\brief enable SAM_V interface timeout detect
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_sam_timeout_enable(uint32_t i2c_periph)
|
|
{
|
|
I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN;
|
|
}
|
|
|
|
/*!
|
|
\brief disable SAM_V interface timeout detect
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_sam_timeout_disable(uint32_t i2c_periph)
|
|
{
|
|
I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN);
|
|
}
|
|
|
|
/*!
|
|
\brief check I2C flag is set or not
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] flag: I2C flags, refer to i2c_flag_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_FLAG_SBSEND: start condition send out
|
|
\arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
|
|
\arg I2C_FLAG_BTC: byte transmission finishes
|
|
\arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
|
|
\arg I2C_FLAG_STPDET: stop condition detected in slave mode
|
|
\arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
|
|
\arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting
|
|
\arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
|
|
\arg I2C_FLAG_LOSTARB: arbitration lost in master mode
|
|
\arg I2C_FLAG_AERR: acknowledge error
|
|
\arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
|
|
\arg I2C_FLAG_PECERR: PEC error when receiving data
|
|
\arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
|
|
\arg I2C_FLAG_SMBALT: SMBus alert status
|
|
\arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
|
|
\arg I2C_FLAG_I2CBSY: busy flag
|
|
\arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver
|
|
\arg I2C_FLAG_RXGC: general call address (00h) received
|
|
\arg I2C_FLAG_DEFSMB: default address of SMBus device
|
|
\arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
|
|
\arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode
|
|
\arg I2C_FLAG_TFF: txframe fall flag
|
|
\arg I2C_FLAG_TFR: txframe rise flag
|
|
\arg I2C_FLAG_RFF: rxframe fall flag
|
|
\arg I2C_FLAG_RFR: rxframe rise flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
|
|
{
|
|
if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief clear I2C flag
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] flag: I2C flags, refer to i2c_flag_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_FLAG_SMBALT: SMBus Alert status
|
|
\arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
|
|
\arg I2C_FLAG_PECERR: PEC error when receiving data
|
|
\arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
|
|
\arg I2C_FLAG_AERR: acknowledge error
|
|
\arg I2C_FLAG_LOSTARB: arbitration lost in master mode
|
|
\arg I2C_FLAG_BERR: a bus error
|
|
\arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
|
|
\arg I2C_FLAG_TFF: txframe fall flag
|
|
\arg I2C_FLAG_TFR: txframe rise flag
|
|
\arg I2C_FLAG_RFF: rxframe fall flag
|
|
\arg I2C_FLAG_RFR: rxframe rise flag
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag)
|
|
{
|
|
if(I2C_FLAG_ADDSEND == flag){
|
|
/* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
|
|
I2C_STAT0(i2c_periph);
|
|
I2C_STAT1(i2c_periph);
|
|
}else{
|
|
I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag));
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief enable I2C interrupt
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_INT_ERR: error interrupt enable
|
|
\arg I2C_INT_EV: event interrupt enable
|
|
\arg I2C_INT_BUF: buffer interrupt enable
|
|
\arg I2C_INT_TFF: txframe fall interrupt enable
|
|
\arg I2C_INT_TFR: txframe rise interrupt enable
|
|
\arg I2C_INT_RFF: rxframe fall interrupt enable
|
|
\arg I2C_INT_RFR: rxframe rise interrupt enable
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
|
|
{
|
|
I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt));
|
|
}
|
|
|
|
/*!
|
|
\brief disable I2C interrupt
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] interrupt: I2C interrupts, refer to i2c_flag_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_INT_ERR: error interrupt enable
|
|
\arg I2C_INT_EV: event interrupt enable
|
|
\arg I2C_INT_BUF: buffer interrupt enable
|
|
\arg I2C_INT_TFF: txframe fall interrupt enable
|
|
\arg I2C_INT_TFR: txframe rise interrupt enable
|
|
\arg I2C_INT_RFF: rxframe fall interrupt enable
|
|
\arg I2C_INT_RFR: rxframe rise interrupt enable
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
|
|
{
|
|
I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt));
|
|
}
|
|
|
|
/*!
|
|
\brief check I2C interrupt flag
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
|
|
\arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
|
|
\arg I2C_INT_FLAG_BTC: byte transmission finishes
|
|
\arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
|
|
\arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
|
|
\arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
|
|
\arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
|
|
\arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
|
|
\arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
|
|
\arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
|
|
\arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
|
|
\arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
|
|
\arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
|
|
\arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
|
|
\arg I2C_INT_FLAG_TFF: txframe fall interrupt flag
|
|
\arg I2C_INT_FLAG_TFR: txframe rise interrupt flag
|
|
\arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag
|
|
\arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
|
|
{
|
|
uint32_t intenable = 0U, flagstatus = 0U, bufie;
|
|
|
|
/* check BUFIE */
|
|
bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE;
|
|
|
|
/* get the interrupt enable bit status */
|
|
intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag)));
|
|
/* get the corresponding flag bit status */
|
|
flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag)));
|
|
|
|
if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){
|
|
if(intenable && bufie){
|
|
intenable = 1U;
|
|
}else{
|
|
intenable = 0U;
|
|
}
|
|
}
|
|
if((0U != flagstatus) && (0U != intenable)){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief clear I2C interrupt flag
|
|
\param[in] i2c_periph: I2Cx(x=0,1)
|
|
\param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
|
|
\arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
|
|
\arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag
|
|
\arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag
|
|
\arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
|
|
\arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
|
|
\arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
|
|
\arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
|
|
\arg I2C_INT_FLAG_TFF: txframe fall interrupt flag
|
|
\arg I2C_INT_FLAG_TFR: txframe rise interrupt flag
|
|
\arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag
|
|
\arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag)
|
|
{
|
|
if(I2C_INT_FLAG_ADDSEND == int_flag){
|
|
/* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */
|
|
I2C_STAT0(i2c_periph);
|
|
I2C_STAT1(i2c_periph);
|
|
}else{
|
|
I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag));
|
|
}
|
|
}
|