390 lines
25 KiB
C
390 lines
25 KiB
C
/*!
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\file gd32e230_i2c.h
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\brief definitions for the I2C
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\version 2018-06-19, V1.0.0, firmware for GD32E230
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32E230_I2C_H
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#define GD32E230_I2C_H
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#include "gd32e230.h"
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/* I2Cx(x=0,1) definitions */
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#define I2C0 I2C_BASE /*!< I2C0 base address */
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#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */
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/* registers definitions */
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#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */
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#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */
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#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/
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#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */
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#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */
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#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */
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#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */
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#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */
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#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */
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#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */
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#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */
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/* bits definitions */
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/* I2Cx_CTL0 */
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#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
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#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
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#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
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#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
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#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
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#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
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#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
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#define I2C_CTL0_START BIT(8) /*!< start generation */
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#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
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#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
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#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
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#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
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#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
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#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
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/* I2Cx_CTL1 */
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#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */
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#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */
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#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
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#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
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#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
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#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
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/* I2Cx_SADDR0 */
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#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
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#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
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#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
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#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
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/* I2Cx_SADDR1 */
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#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
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#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
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/* I2Cx_DATA */
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#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
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/* I2Cx_STAT0 */
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#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
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#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
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#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
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#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
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#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
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#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
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#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
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#define I2C_STAT0_BERR BIT(8) /*!< bus error */
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#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
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#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
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#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
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#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
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#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
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#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
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/* I2Cx_STAT1 */
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#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
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#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
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#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
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#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
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#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
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#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
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#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
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#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
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/* I2Cx_CKCFG */
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#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
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#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */
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#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
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/* I2Cx_RT */
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#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
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/* I2Cx_SAMCS */
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#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
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#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
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#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
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#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
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#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
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#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
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#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
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#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
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#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */
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#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */
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#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */
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#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */
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/* I2Cx_FMPCFG */
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#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */
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/* constants definitions */
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/* define the I2C bit position and its register index offset */
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#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
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#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
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#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
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| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
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#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
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#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
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/* register offset */
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#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
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#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */
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#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */
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#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */
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/* I2C flags */
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typedef enum
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{
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/* flags in STAT0 register */
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I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
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I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
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I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
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I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
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I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
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I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
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I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
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I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
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I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
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I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
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I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
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I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
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I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
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I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
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/* flags in STAT1 register */
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I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
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I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
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I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
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I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
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I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
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I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
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I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
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/* flags in SAMCS register */
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I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
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I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
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I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
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I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
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}i2c_flag_enum;
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/* I2C interrupt flags */
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typedef enum
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{
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/* interrupt flags in CTL1 register */
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I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
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I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
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I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
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I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
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I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
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I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
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I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
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I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
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I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
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I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
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I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
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I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
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I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
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I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
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/* interrupt flags in SAMCS register */
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I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
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I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
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I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
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I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
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}i2c_interrupt_flag_enum;
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/* I2C interrupt enable or disable */
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typedef enum
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{
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/* interrupt in CTL1 register */
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I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
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I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
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I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
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/* interrupt in SAMCS register */
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I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */
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I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */
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I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */
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I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */
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}i2c_interrupt_enum;
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/* SMBus/I2C mode switch and SMBus type selection */
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#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
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#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
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/* SMBus/I2C mode switch and SMBus type selection */
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#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
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#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
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/* I2C transfer direction */
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#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
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#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
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/* whether or not to send an ACK */
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#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
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#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
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/* I2C POAP position*/
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#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
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#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
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/* whether or not to stretch SCL low */
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#define I2C_SCLSTRETCH_ENABLE I2C_CTL0_SS /*!< SCL stretching is enabled */
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#define I2C_SCLSTRETCH_DISABLE ((uint32_t)0x00000000U) /*!< SCL stretching is disabled */
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/* whether or not to response to a general call */
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#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
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#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
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/* software reset I2C */
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#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
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#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
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/* I2C DMA mode configure */
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/* DMA mode switch */
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#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
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#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
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/* flag indicating DMA last transfer */
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#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
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#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
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/* I2C PEC configure */
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/* PEC enable */
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#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
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#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
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/* PEC transfer */
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#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
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#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
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/* I2C SMBus configure */
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/* issue or not alert through SMBA pin */
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#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
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#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
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/* ARP protocol in SMBus switch */
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#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */
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#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */
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/* fast mode plus enable */
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#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */
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#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */
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/* transmit I2C data */
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#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
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/* receive I2C data */
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#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
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/* I2C duty cycle in fast mode or fast mode plus */
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#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */
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#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */
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/* address mode for the I2C slave */
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#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
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#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
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/* function declarations */
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/* reset I2C */
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void i2c_deinit(uint32_t i2c_periph);
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/* configure I2C clock */
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void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
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/* configure I2C address */
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void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
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/* SMBus type selection */
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void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
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/* whether or not to send an ACK */
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void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
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/* configure I2C POAP position */
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void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
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/* master sends slave address */
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void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
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/* enable dual-address mode */
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void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
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/* disable dual-address mode */
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void i2c_dualaddr_disable(uint32_t i2c_periph);
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/* enable I2C */
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void i2c_enable(uint32_t i2c_periph);
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/* disable I2C */
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void i2c_disable(uint32_t i2c_periph);
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/* generate a START condition on I2C bus */
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void i2c_start_on_bus(uint32_t i2c_periph);
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/* generate a STOP condition on I2C bus */
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void i2c_stop_on_bus(uint32_t i2c_periph);
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/* I2C transmit data function */
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void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
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/* I2C receive data function */
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uint8_t i2c_data_receive(uint32_t i2c_periph);
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/* enable I2C DMA mode */
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void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
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/* configure whether next DMA EOT is DMA last transfer or not */
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void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
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/* whether to stretch SCL low when data is not ready in slave mode */
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void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
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/* whether or not to response to a general call */
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void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
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/* software reset I2C */
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void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
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/* I2C PEC calculation on or off */
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void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
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/* I2C whether to transfer PEC value */
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void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
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/* packet error checking value */
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uint8_t i2c_pec_value_get(uint32_t i2c_periph);
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/* I2C issue alert through SMBA pin */
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void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
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/* I2C ARP protocol in SMBus switch */
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void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
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/* enable SAM_V interface */
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void i2c_sam_enable(uint32_t i2c_periph);
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/* disable SAM_V interface */
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void i2c_sam_disable(uint32_t i2c_periph);
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/* enable SAM_V interface timeout detect */
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void i2c_sam_timeout_enable(uint32_t i2c_periph);
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/* disable SAM_V interface timeout detect */
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void i2c_sam_timeout_disable(uint32_t i2c_periph);
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/* check I2C flag is set or not */
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FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
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/* clear I2C flag */
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void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
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/* enable I2C interrupt */
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void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
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/* disable I2C interrupt */
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void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
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/* check I2C interrupt flag */
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FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
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/* clear I2C interrupt flag */
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void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
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#endif /* GD32E230_I2C_H */
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