114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-12-02 bigmagic first version
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*/
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#include "drv_dma.h"
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#include "raspi4.h"
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volatile unsigned int __attribute__((aligned(256))) dma_disc[32];
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//https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=10276
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static struct rt_semaphore dma_sem;
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//DMA 0 1 2 3 4 5 6
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typedef struct _dma_ctrl_block
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{
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unsigned int TI; // Transfer information
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unsigned int SOURCE_AD; // source address
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unsigned int DEST_AD; // destination address
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unsigned int TXFR_LEN; // transfer length
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unsigned int STRIDE; // 2D mode stride
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struct _dma_ctrl_block *NEXTCONBK; // Next control block address
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unsigned int DEBUG;
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unsigned int reserved1;
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} dma_ctrl_block_t;
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//DMA 7 8 9 10
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typedef struct _dma_lite_ctrl_block
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{
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unsigned int TI; // Transfer information
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unsigned int SOURCE_AD; // source address
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unsigned int DEST_AD; // destination address
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unsigned int TXFR_LEN; // transfer length
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struct _dma_lite_ctrl_block *NEXTCONBK; // Next control block address
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unsigned int DEBUG;
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unsigned int reserved1;
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unsigned int reserved2;
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} dma_lite_ctrl_block_t;
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//DMA 11 12 13 14 15
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typedef struct _dma4_ctrl_block
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{
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unsigned int TI; // Transfer information
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unsigned int SOURCE_AD0; // source address0
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unsigned int SOURCE_AD1; // source address1
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unsigned int DEST_AD0; // destination address0
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unsigned int DEST_AD1; // destination address1
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unsigned int TXFR_LEN; // transfer length
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unsigned int STRIDE; // 2D mode stride
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struct _dma4_ctrl_block *NEXTCONBK; // Next control block address
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} dma4_ctrl_block_t;
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static dma_lite_ctrl_block_t *ctr_blocks;
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static void dma_irq(int irq, void *param)
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{
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if (DMA_INT_STATUS_REG & DMA_INT7)
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{
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DMA_CS(7) = DMA_CS_INT;
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rt_sem_release(&dma_sem);
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}
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}
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//dma 7 8 9 10:XLENGTH
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rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout)
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{
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, dst, size);
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/* Stop DMA, if it was already started */
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DMA_CS(dch) = DMA_CS_RESET;
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/* Clear DMA status flags */
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DMA_CS(dch) = DMA_CS_INT | DMA_CS_END; /* Interrupted flag & Transmission ended flag*/
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//cb info
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ctr_blocks->TI = DMA_TI_SRC_INC | DMA_TI_DEST_INC | DMA_TI_INTEN;
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ctr_blocks->SOURCE_AD = (unsigned int)src;
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ctr_blocks->DEST_AD = (unsigned int)dst;
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ctr_blocks->TXFR_LEN = size;
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ctr_blocks->NEXTCONBK = 0;
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ctr_blocks->reserved1 = 0;
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ctr_blocks->reserved2 = 0;
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ctr_blocks, sizeof(dma_lite_ctrl_block_t) * 8);
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DMA_CONBLK_AD(dch) = (rt_uint32_t)ctr_blocks;
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DMA_CS(dch) = DMA_CS_INT | DMA_CS_END | DMA_CS_ACTIVE;
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if(rt_sem_take(&dma_sem, timeout) != RT_EOK)
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{
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rt_kprintf("dma transfer timeout!\n");
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return RT_ERROR;
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}
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return RT_EOK;
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}
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void dma_init(unsigned char dch)
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{
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rt_sem_init(&dma_sem, "dma_sem", 0, RT_IPC_FLAG_FIFO);
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ctr_blocks = (dma_lite_ctrl_block_t *)&dma_disc[0]; //rt_malloc(sizeof(DMA_Lite_Control_Block));
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//Make sure DMA channel is enabled by
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//writing the corresponding bit in DMA_ENABLE in the DMA register to 1
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DMA_ENABLE_REG = (1 << dch);
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rt_hw_interrupt_install(IRQ_DMA7_DMA8, dma_irq, RT_NULL, "dma_irq");
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rt_hw_interrupt_umask(IRQ_DMA7_DMA8);
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}
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