458 lines
17 KiB
C
458 lines
17 KiB
C
/***************************************************************************//**
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* @file
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* @brief Direct memory access (DMA) API for EFM32.
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* @author Energy Micro AS
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* @version 2.3.2
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#ifndef __EFM32_DMA_H
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#define __EFM32_DMA_H
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#include <stdio.h>
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#include <stdbool.h>
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#include "efm32.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup DMA
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* @{
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******************************************************************************/
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/*******************************************************************************
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******************************** ENUMS ************************************
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******************************************************************************/
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/**
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* Amount source/destination address should be incremented for each data
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* transfer.
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*/
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typedef enum
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{
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dmaDataInc1 = _DMA_CTRL_SRC_INC_BYTE, /**< Increment address 1 byte. */
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dmaDataInc2 = _DMA_CTRL_SRC_INC_HALFWORD, /**< Increment address 2 bytes. */
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dmaDataInc4 = _DMA_CTRL_SRC_INC_WORD, /**< Increment address 4 bytes. */
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dmaDataIncNone = _DMA_CTRL_SRC_INC_NONE /**< Do not increment address. */
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} DMA_DataInc_TypeDef;
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/** Data sizes (in number of bytes) to be read/written by DMA transfer. */
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typedef enum
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{
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dmaDataSize1 = _DMA_CTRL_SRC_SIZE_BYTE, /**< 1 byte DMA transfer size. */
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dmaDataSize2 = _DMA_CTRL_SRC_SIZE_HALFWORD, /**< 2 byte DMA transfer size. */
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dmaDataSize4 = _DMA_CTRL_SRC_SIZE_WORD /**< 4 byte DMA transfer size. */
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} DMA_DataSize_TypeDef;
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/** Type of DMA transfer. */
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typedef enum
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{
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/** Basic DMA cycle. */
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dmaCycleCtrlBasic = _DMA_CTRL_CYCLE_CTRL_BASIC,
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/** Auto-request DMA cycle. */
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dmaCycleCtrlAuto = _DMA_CTRL_CYCLE_CTRL_AUTO,
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/** Ping-pong DMA cycle. */
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dmaCycleCtrlPingPong = _DMA_CTRL_CYCLE_CTRL_PINGPONG,
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/** Memory scatter-gather DMA cycle. */
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dmaCycleCtrlMemScatterGather = _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER,
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/** Peripheral scatter-gather DMA cycle. */
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dmaCycleCtrlPerScatterGather = _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER
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} DMA_CycleCtrl_TypeDef;
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/** Number of transfers before controller does new arbitration. */
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typedef enum
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{
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dmaArbitrate1 = _DMA_CTRL_R_POWER_1, /**< Arbitrate after 1 DMA transfer. */
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dmaArbitrate2 = _DMA_CTRL_R_POWER_2, /**< Arbitrate after 2 DMA transfers. */
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dmaArbitrate4 = _DMA_CTRL_R_POWER_4, /**< Arbitrate after 4 DMA transfers. */
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dmaArbitrate8 = _DMA_CTRL_R_POWER_8, /**< Arbitrate after 8 DMA transfers. */
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dmaArbitrate16 = _DMA_CTRL_R_POWER_16, /**< Arbitrate after 16 DMA transfers. */
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dmaArbitrate32 = _DMA_CTRL_R_POWER_32, /**< Arbitrate after 32 DMA transfers. */
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dmaArbitrate64 = _DMA_CTRL_R_POWER_64, /**< Arbitrate after 64 DMA transfers. */
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dmaArbitrate128 = _DMA_CTRL_R_POWER_128, /**< Arbitrate after 128 DMA transfers. */
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dmaArbitrate256 = _DMA_CTRL_R_POWER_256, /**< Arbitrate after 256 DMA transfers. */
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dmaArbitrate512 = _DMA_CTRL_R_POWER_512, /**< Arbitrate after 512 DMA transfers. */
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dmaArbitrate1024 = _DMA_CTRL_R_POWER_1024 /**< Arbitrate after 1024 DMA transfers. */
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} DMA_ArbiterConfig_TypeDef;
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/*******************************************************************************
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******************************* STRUCTS ***********************************
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******************************************************************************/
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/**
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* @brief
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* DMA interrupt callback function pointer.
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* @details
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* Parameters:
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* @li channel - The DMA channel the callback function is invoked for.
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* @li primary - Indicates if callback is invoked for completion of primary
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* (true) or alternate (false) descriptor. This is mainly useful for
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* ping-pong DMA cycles, in order to know which descriptor to refresh.
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* @li user - User definable reference that may be used to pass information
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* to be used by the callback handler. If used, the referenced data must be
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* valid at the point when the interrupt handler invokes the callback.
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* If callback changes any data in the provided user structure, remember
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* that those changes are done in interrupt context, and proper protection
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* of data may be required.
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*/
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typedef void (*DMA_FuncPtr_TypeDef)(unsigned int channel, bool primary, void *user);
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/**
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* @brief
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* Callback structure that can be used to define DMA complete actions.
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* @details
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* A reference to this structure is only stored in the primary descriptor
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* for a channel (if callback feature is used). If callback is required
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* for both primary and alternate descriptor completion, this must be
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* handled by one common callback, using the provided 'primary' parameter
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* with the callback function.
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*/
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typedef struct
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{
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/**
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* Pointer to callback function to invoke when DMA transfer cycle done.
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* Notice that this function is invoked in interrupt context, and therefore
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* should be short and non-blocking.
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*/
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DMA_FuncPtr_TypeDef cbFunc;
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/** User defined pointer to provide with callback function. */
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void *userPtr;
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/**
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* For internal use only: Indicates if next callback applies to primary
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* or alternate descriptor completion. Mainly useful for ping-pong DMA
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* cycles. Set this value to 0 prior to configuring callback handling.
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*/
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uint8_t primary;
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} DMA_CB_TypeDef;
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/** Configuration structure for a channel. */
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typedef struct
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{
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/**
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* Select if channel priority is in the high or default priority group
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* with respect to arbitration. Within a priority group, lower numbered
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* channels have higher priority than higher numbered channels.
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*/
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bool highPri;
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/**
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* Select if interrupt shall be enabled for channel (triggering interrupt
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* handler when dma_done signal is asserted). It should normally be
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* enabled if using the callback feature for a channel, and disabled if
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* not using the callback feature.
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*/
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bool enableInt;
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/**
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* Channel control specifying the source of DMA signals. If accessing
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* peripherals, use one of the DMAREQ_nnn defines available for the
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* peripheral. Set it to 0 for memory-to-memory DMA cycles.
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*/
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uint32_t select;
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/**
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* @brief
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* User definable callback handling configuration.
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* @details
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* Please refer to structure definition for details. The callback
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* is invoked when the specified DMA cycle is complete (when dma_done
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* signal asserted). The callback is invoked in interrupt context,
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* and should be efficient and non-blocking. Set to NULL to not
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* use the callback feature.
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* @note
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* The referenced structure is used by the interrupt handler, and must
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* be available until no longer used. Thus, in most cases it should
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* not be located on the stack.
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*/
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DMA_CB_TypeDef *cb;
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} DMA_CfgChannel_TypeDef;
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/**
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* Configuration structure for primary or alternate descriptor
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* (not used for scatter-gather DMA cycles).
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*/
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typedef struct
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{
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/** Destination increment size for each DMA transfer */
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DMA_DataInc_TypeDef dstInc;
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/** Source increment size for each DMA transfer */
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DMA_DataInc_TypeDef srcInc;
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/** DMA transfer unit size. */
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DMA_DataSize_TypeDef size;
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/**
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* Arbitration rate, ie number of DMA transfers done before rearbitration
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* takes place.
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*/
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DMA_ArbiterConfig_TypeDef arbRate;
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/**
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* HPROT signal state, please refer to reference manual, DMA chapter for
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* further details. Normally set to 0 if protection is not an issue.
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* The following bits are available:
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* @li bit 0 - HPROT[1] control for source read accesses,
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* privileged/non-privileged access
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* @li bit 3 - HPROT[1] control for destination write accesses,
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* privileged/non-privileged access
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*/
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uint8_t hprot;
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} DMA_CfgDescr_TypeDef;
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#if defined(_EFM32_GIANT_FAMILY)
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/**
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* Configuration structure for loop mode
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*/
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typedef struct
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{
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/** Enable repeated loop */
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bool enable;
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/** Width of transfer, reload value for nMinus1 */
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uint16_t nMinus1;
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} DMA_CfgLoop_TypeDef;
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/**
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* Configuration structure for rectangular copy
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*/
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typedef struct
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{
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/** DMA channel destination stride (width of destination image, distance between lines) */
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uint16_t dstStride;
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/** DMA channel source stride (width of source image, distance between lines) */
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uint16_t srcStride;
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/** 2D copy height */
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uint16_t height;
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} DMA_CfgRect_TypeDef;
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#endif
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/** Configuration structure for alternate scatter-gather descriptor. */
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typedef struct
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{
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/** Pointer to location to transfer data from. */
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void *src;
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/** Pointer to location to transfer data to. */
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void *dst;
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/** Destination increment size for each DMA transfer */
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DMA_DataInc_TypeDef dstInc;
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/** Source increment size for each DMA transfer */
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DMA_DataInc_TypeDef srcInc;
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/** DMA transfer unit size. */
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DMA_DataSize_TypeDef size;
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/**
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* Arbitration rate, ie number of DMA transfers done before rearbitration
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* takes place.
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*/
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DMA_ArbiterConfig_TypeDef arbRate;
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/** Number of DMA transfers minus 1 to do. Must be <= 1023. */
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uint16_t nMinus1;
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/**
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* HPROT signal state, please refer to reference manual, DMA chapter for
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* further details. Normally set to 0 if protection is not an issue.
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* The following bits are available:
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* @li bit 0 - HPROT[1] control for source read accesses,
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* privileged/non-privileged access
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* @li bit 3 - HPROT[1] control for destination write accesses,
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* privileged/non-privileged access
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*/
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uint8_t hprot;
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/** Specify if a memory or peripheral scatter-gather DMA cycle. Notice
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* that this parameter should be the same for all alternate
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* descriptors.
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* @li true - this is a peripheral scatter-gather cycle
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* @li false - this is a memory scatter-gather cycle
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*/
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bool peripheral;
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} DMA_CfgDescrSGAlt_TypeDef;
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/** DMA init structure */
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typedef struct
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{
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/**
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* HPROT signal state when accessing the primary/alternate
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* descriptors. Normally set to 0 if protection is not an issue.
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* The following bits are available:
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* @li bit 0 - HPROT[1] control for descriptor accesses (ie when
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* the DMA controller accesses the channel control block itself),
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* privileged/non-privileged access
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*/
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uint8_t hprot;
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/**
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* Pointer to the controlblock in memory holding descriptors (channel
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* control data structures). This memory must be properly aligned
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* according to requirements.
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*
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* Alignment requirements are
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* a) 5 bits base requirement, bits [4:0]
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* b) Add the number of bits needed to represent the wanted number
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* of channels
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* c) Align structure with this number of bits set to zero
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*
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* Examples: 4 channels, 5 + 2 (channels 0 to 3) = 7 bits
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* 7 bit alignment, 64 byte address alignment
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* 8 channels, 5 + 3 (channels 0 to 7) = 8 bits
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* 8 bit alignment, 256 byte address alignment
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* 12 channels, 5 + 4 (channels 0 to 11) = 9 bits
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* 9 bit alignment, 512 byte address alignment
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*
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* Please refer to the reference manual, DMA chapter for more details.
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*
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* It is possible to provide a smaller memory block, only covering
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* those channels actually used, if not all available channels are used.
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* Ie, if only using 4 channels (0-3), both primary and alternate
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* structures, then only 16*2*4 = 128 bytes must be provided. This
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* implementation has however no check if later exceeding such a limit
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* by configuring for instance channel 4, in which case memory overwrite
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* of some other data will occur.
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*/
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DMA_DESCRIPTOR_TypeDef *controlBlock;
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} DMA_Init_TypeDef;
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/*******************************************************************************
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***************************** PROTOTYPES **********************************
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******************************************************************************/
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void DMA_ActivateAuto(unsigned int channel,
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bool primary,
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void *dst,
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void *src,
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unsigned int nMinus1);
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void DMA_ActivateBasic(unsigned int channel,
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bool primary,
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bool useBurst,
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void *dst,
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void *src,
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unsigned int nMinus1);
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void DMA_ActivatePingPong(unsigned int channel,
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bool useBurst,
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void *primDst,
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void *primSrc,
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unsigned int primNMinus1,
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void *altDst,
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void *altSrc,
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unsigned int altNMinus1);
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void DMA_ActivateScatterGather(unsigned int channel,
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bool useBurst,
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DMA_DESCRIPTOR_TypeDef *altDescr,
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unsigned int count);
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void DMA_CfgChannel(unsigned int channel, DMA_CfgChannel_TypeDef *cfg);
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void DMA_CfgDescr(unsigned int channel,
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bool primary,
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DMA_CfgDescr_TypeDef *cfg);
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#if defined(_EFM32_GIANT_FAMILY)
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void DMA_CfgLoop(unsigned int channel, DMA_CfgLoop_TypeDef *cfg);
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void DMA_CfgRect(unsigned int channel, DMA_CfgRect_TypeDef *cfg);
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/***************************************************************************//**
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* @brief
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* Clear Loop configuration for channel
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*
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* @param[in] channel
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* Channel to reset loop configuration for
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******************************************************************************/
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static __INLINE void DMA_ResetLoop(unsigned int channel)
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{
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/* Clean loop copy operation */
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switch(channel)
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{
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case 0:
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DMA->LOOP0 = _DMA_LOOP0_RESETVALUE;
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break;
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case 1:
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DMA->LOOP1 = _DMA_LOOP1_RESETVALUE;
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break;
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default:
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break;
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}
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}
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/***************************************************************************//**
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* @brief
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* Clear Rect/2D DMA configuration for channel
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*
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* @param[in] channel
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* Channel to reset loop configuration for
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******************************************************************************/
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static __INLINE void DMA_ResetRect(unsigned int channel)
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{
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(void) channel;
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/* Clear rect copy operation */
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DMA->RECT0 = _DMA_RECT0_RESETVALUE;
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}
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#endif
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void DMA_CfgDescrScatterGather(DMA_DESCRIPTOR_TypeDef *descr,
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unsigned int indx,
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DMA_CfgDescrSGAlt_TypeDef *cfg);
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bool DMA_ChannelEnabled(unsigned int channel);
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void DMA_Init(DMA_Init_TypeDef *init);
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void DMA_IRQHandler(void);
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void DMA_RefreshPingPong(unsigned int channel,
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bool primary,
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bool useBurst,
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void *dst,
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void *src,
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unsigned int nMinus1,
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bool last);
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void DMA_Reset(void);
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/** @} (end addtogroup DMA) */
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/** @} (end addtogroup EFM32_Library) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EFM32_DMA_H */
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