221 lines
7.5 KiB
INI
221 lines
7.5 KiB
INI
# Copyright (c) 2023 HPMicro
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# SPDX-License-Identifier: BSD-3-Clause
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flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7
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proc init_clock {} {
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$::_TARGET0 riscv dmi_write 0x39 0xF4000800
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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$::_TARGET0 riscv dmi_write 0x39 0xF4000810
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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$::_TARGET0 riscv dmi_write 0x39 0xF4000820
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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$::_TARGET0 riscv dmi_write 0x39 0xF4000830
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$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
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echo "clocks has been enabled!"
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}
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proc init_ddr3 {} {
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# ddr dcdc setup
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$::_TARGET0 riscv dmi_write 0x39 0xF4104080
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$::_TARGET0 riscv dmi_write 0x3C 0x10578
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# ddr3 setup
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$::_TARGET0 riscv dmi_write 0x39 0xF40C0180
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$::_TARGET0 riscv dmi_write 0x3C 0x30000019
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$::_TARGET0 riscv dmi_write 0x39 0xF400180C
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$::_TARGET0 riscv dmi_write 0x3C 0x09100401
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$::_TARGET0 riscv dmi_write 0x39 0xF4153000
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$::_TARGET0 riscv dmi_write 0x3C 0xF0000010
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$::_TARGET0 riscv dmi_write 0x39 0xF30101B0
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF4150040
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$::_TARGET0 riscv dmi_write 0x3C 0xf004641f
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$::_TARGET0 riscv dmi_write 0x39 0xF4153000
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$::_TARGET0 riscv dmi_write 0x3C 0xf0000011
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$::_TARGET0 riscv dmi_write 0x39 0xF3013000
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$::_TARGET0 riscv dmi_write 0x3C 0xf4000000
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$::_TARGET0 riscv dmi_write 0x39 0xF3010490
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$::_TARGET0 riscv dmi_write 0x3C 1
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$::_TARGET0 riscv dmi_write 0x39 0xF3010000
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$::_TARGET0 riscv dmi_write 0x3C 0x1040001
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$::_TARGET0 riscv dmi_write 0x39 0xF30100D0
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$::_TARGET0 riscv dmi_write 0x3C 0x4002004e
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$::_TARGET0 riscv dmi_write 0x39 0xF3010110
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$::_TARGET0 riscv dmi_write 0x3C 0x05010407
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$::_TARGET0 riscv dmi_write 0x39 0xF3010190
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$::_TARGET0 riscv dmi_write 0x3C 0x07040102
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$::_TARGET0 riscv dmi_write 0x39 0xF3010194
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$::_TARGET0 riscv dmi_write 0x3C 0x20404
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$::_TARGET0 riscv dmi_write 0x39 0xF30101A4
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$::_TARGET0 riscv dmi_write 0x3C 0x20008
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$::_TARGET0 riscv dmi_write 0x39 0xF3010240
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$::_TARGET0 riscv dmi_write 0x3C 0x06000600
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$::_TARGET0 riscv dmi_write 0x39 0xF3010200
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$::_TARGET0 riscv dmi_write 0x3C 0x1F1F1F
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$::_TARGET0 riscv dmi_write 0x39 0xF3010204
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$::_TARGET0 riscv dmi_write 0x3C 0x121212
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$::_TARGET0 riscv dmi_write 0x39 0xF3010208
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF301020C
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF3010210
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$::_TARGET0 riscv dmi_write 0x3C 0x1F1F
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$::_TARGET0 riscv dmi_write 0x39 0xF3010214
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$::_TARGET0 riscv dmi_write 0x3C 0x06030303
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$::_TARGET0 riscv dmi_write 0x39 0xF3010218
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$::_TARGET0 riscv dmi_write 0x3C 0x0F060606
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$::_TARGET0 riscv dmi_write 0x39 0xF3013000
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$::_TARGET0 riscv dmi_write 0x3C 0xFC000000
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$::_TARGET0 riscv dmi_write 0x39 0xF4150054
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$::_TARGET0 riscv dmi_write 0x3C 0xc70
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$::_TARGET0 riscv dmi_write 0x39 0xF4150058
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$::_TARGET0 riscv dmi_write 0x3C 0x6
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$::_TARGET0 riscv dmi_write 0x39 0xF415005c
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$::_TARGET0 riscv dmi_write 0x3C 0x18
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$::_TARGET0 riscv dmi_write 0x39 0xF4150048
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$::_TARGET0 riscv dmi_write 0x3C 0x919c8866
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$::_TARGET0 riscv dmi_write 0x39 0xF415004c
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$::_TARGET0 riscv dmi_write 0x3C 0x1a838360
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$::_TARGET0 riscv dmi_write 0x39 0xF415008c
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$::_TARGET0 riscv dmi_write 0x3C 0xf06d50
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$::_TARGET0 riscv dmi_write 0x39 0xF4150050
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$::_TARGET0 riscv dmi_write 0x3C 0x3002d200
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$::_TARGET0 riscv dmi_write 0x39 0xF30101b0
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$::_TARGET0 riscv dmi_write 0x3C 1
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sleep 100
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$::_TARGET0 riscv dmi_write 0x39 0xF4150068
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$::_TARGET0 riscv dmi_write 0x3C 0x930035C7
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$::_TARGET0 riscv dmi_write 0x39 0xF4150004
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$::_TARGET0 riscv dmi_write 0x3C 0xFF81
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sleep 200
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echo "ddr3 has been enabled!"
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}
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proc init_dram {} {
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# ddr dcdc setup
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$::_TARGET0 riscv dmi_write 0x39 0xF4104080
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$::_TARGET0 riscv dmi_write 0x3C 0x10708
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# pll1 setup
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$::_TARGET0 riscv dmi_write 0x39 0xF40c0180
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$::_TARGET0 riscv dmi_write 0x3C 0xb0000016
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$::_TARGET0 riscv dmi_write 0x39 0xF40c0184
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF40c0188
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$::_TARGET0 riscv dmi_write 0x3C 0xe4e1c00
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#ddr setup
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$::_TARGET0 riscv dmi_write 0x39 0xF3010000
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$::_TARGET0 riscv dmi_write 0x3C 0x3040000
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$::_TARGET0 riscv dmi_write 0x39 0xF30101B0
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF4150044
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$::_TARGET0 riscv dmi_write 0x3C 0x40a
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$::_TARGET0 riscv dmi_write 0x39 0xF4150040
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$::_TARGET0 riscv dmi_write 0x3C 0xf004641f
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$::_TARGET0 riscv dmi_write 0x39 0xF4153000
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$::_TARGET0 riscv dmi_write 0x3C 0xf0000011
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$::_TARGET0 riscv dmi_write 0x39 0xF3013000
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$::_TARGET0 riscv dmi_write 0x3C 0xf4000000
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$::_TARGET0 riscv dmi_write 0x39 0xF3010490
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$::_TARGET0 riscv dmi_write 0x3C 1
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$::_TARGET0 riscv dmi_write 0x39 0xF3010000
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$::_TARGET0 riscv dmi_write 0x3C 0x1040000
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$::_TARGET0 riscv dmi_write 0x39 0xF3010190
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$::_TARGET0 riscv dmi_write 0x3C 0x07010101
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$::_TARGET0 riscv dmi_write 0x39 0xF3010194
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$::_TARGET0 riscv dmi_write 0x3C 0x20404
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$::_TARGET0 riscv dmi_write 0x39 0xF30101A4
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$::_TARGET0 riscv dmi_write 0x3C 0x20008
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$::_TARGET0 riscv dmi_write 0x39 0xF3010240
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$::_TARGET0 riscv dmi_write 0x3C 0x6000600
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$::_TARGET0 riscv dmi_write 0x39 0xF3010200
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$::_TARGET0 riscv dmi_write 0x3C 0x1f1f1f
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$::_TARGET0 riscv dmi_write 0x39 0xF3010204
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$::_TARGET0 riscv dmi_write 0x3C 0x70707
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$::_TARGET0 riscv dmi_write 0x39 0xF3010208
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF301020c
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF3010210
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$::_TARGET0 riscv dmi_write 0x3C 0x1f1f
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$::_TARGET0 riscv dmi_write 0x39 0xF3010214
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$::_TARGET0 riscv dmi_write 0x3C 0x6060606
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$::_TARGET0 riscv dmi_write 0x39 0xF3010218
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$::_TARGET0 riscv dmi_write 0x3C 0xf0f0606
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$::_TARGET0 riscv dmi_write 0x39 0xF3013000
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$::_TARGET0 riscv dmi_write 0x3C 0xfc000000
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$::_TARGET0 riscv dmi_write 0x39 0xF4150020
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$::_TARGET0 riscv dmi_write 0x3C 0x3000100
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$::_TARGET0 riscv dmi_write 0x39 0xF4150028
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$::_TARGET0 riscv dmi_write 0x3C 0x18002356
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$::_TARGET0 riscv dmi_write 0x39 0xF415002c
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$::_TARGET0 riscv dmi_write 0x3C 0x0aac4156
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$::_TARGET0 riscv dmi_write 0x39 0xF4150054
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$::_TARGET0 riscv dmi_write 0x3C 0xe73
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$::_TARGET0 riscv dmi_write 0x39 0xF4150058
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$::_TARGET0 riscv dmi_write 0x3C 0x5
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$::_TARGET0 riscv dmi_write 0x39 0xF415005c
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$::_TARGET0 riscv dmi_write 0x3C 0
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$::_TARGET0 riscv dmi_write 0x39 0xF4150048
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$::_TARGET0 riscv dmi_write 0x3C 0xf2adfe53
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$::_TARGET0 riscv dmi_write 0x39 0xF415004c
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$::_TARGET0 riscv dmi_write 0x3C 0x22820362
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$::_TARGET0 riscv dmi_write 0x39 0xF4150050
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$::_TARGET0 riscv dmi_write 0x3C 0x30020100
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$::_TARGET0 riscv dmi_write 0x39 0xF415008c
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$::_TARGET0 riscv dmi_write 0x3C 0xf06d50
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$::_TARGET0 riscv dmi_write 0x39 0xF30101b0
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$::_TARGET0 riscv dmi_write 0x3C 1
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sleep 100
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$::_TARGET0 riscv dmi_write 0x39 0xF4150068
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$::_TARGET0 riscv dmi_write 0x3C 0x91003587
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$::_TARGET0 riscv dmi_write 0x39 0xF4150004
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$::_TARGET0 riscv dmi_write 0x3C 0xF501
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sleep 200
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echo "ddr has been enabled!"
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}
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$_TARGET0 configure -event reset-end {
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init_clock
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# init_ddr3
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}
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$_TARGET0 configure -event reset-init {
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init_clock
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init_ddr3
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}
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$_TARGET0 configure -event gdb-attach {
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reset halt
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}
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