104 lines
1.3 KiB
ArmAsm
104 lines
1.3 KiB
ArmAsm
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Date Author Notes
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* 2018-10-06 ZhaoXiaowei the first version
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*/
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.text
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.globl rt_hw_get_current_el
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rt_hw_get_current_el:
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MRS X0, CurrentEL
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CMP X0, 0xc
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B.EQ 3f
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CMP X0, 0x8
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B.EQ 2f
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CMP X0, 0x4
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B.EQ 1f
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LDR X0, =0
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B 0f
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3:
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LDR X0, =3
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B 0f
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2:
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LDR X0, =2
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B 0f
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1:
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LDR X0, =1
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B 0f
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0:
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RET
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.globl rt_hw_set_current_vbar
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rt_hw_set_current_vbar:
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MRS X1, CurrentEL
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CMP X1, 0xc
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B.EQ 3f
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CMP X1, 0x8
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B.EQ 2f
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CMP X1, 0x4
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B.EQ 1f
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B 0f
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3:
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MSR VBAR_EL3,X0
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B 0f
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2:
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MSR VBAR_EL2,X0
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B 0f
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1:
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MSR VBAR_EL1,X0
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B 0f
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0:
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RET
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.globl rt_hw_set_elx_env
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rt_hw_set_elx_env:
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MRS X1, CurrentEL
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CMP X1, 0xc
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B.EQ 3f
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CMP X1, 0x8
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B.EQ 2f
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CMP X1, 0x4
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B.EQ 1f
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B 0f
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3:
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MRS X0, SCR_EL3
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ORR X0, X0, #0xF /* SCR_EL3.NS|IRQ|FIQ|EA */
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MSR SCR_EL3, X0
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B 0f
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2:
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MRS X0, HCR_EL2
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ORR X0, X0, #0x38
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MSR HCR_EL2, X0
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B 0f
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1:
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B 0f
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0:
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RET
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.global rt_cpu_vector_set_base
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rt_cpu_vector_set_base:
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MSR VBAR_EL1,X0
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RET
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/**
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* unsigned long rt_hw_ffz(unsigned long x)
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*/
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.global rt_hw_ffz
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rt_hw_ffz:
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mvn x1, x0
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clz x0, x1
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mov x1, #0x3f
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sub x0, x1, x0
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ret
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.global rt_hw_clz
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rt_hw_clz:
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clz x0, x0
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ret
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