442 lines
18 KiB
C
442 lines
18 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_icg.h
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* @brief This file contains all the Macro Definitions of the ICG driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Yangjp First version
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_ICG_H__
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#define __HC32F4A0_ICG_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_ICG
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* @{
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*/
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#if (DDL_ICG_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup ICG_Global_Macros ICG Global Macros
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* @{
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*/
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/**
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* @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State
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* @{
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*/
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#define ICG_SWDT_RESET_AUTOSTART (0UL) /*!< SWDT Auto Start after reset */
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#define ICG_SWDT_RESET_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_SWDT_Trigger_Type ICG SWDT Trigger Type
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* @{
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*/
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#define ICG_SWDT_TRIG_INT (0UL) /*!< SWDT trigger interrupt */
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#define ICG_SWDT_TRIG_RESET (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_SWDT_Counter_Cycle ICG SWDT Counter Cycle
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* @{
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*/
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#define ICG_SWDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
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#define ICG_SWDT_COUNTER_CYCLE_4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */
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#define ICG_SWDT_COUNTER_CYCLE_16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */
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#define ICG_SWDT_COUNTER_CYCLE_65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division
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* @{
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*/
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#define ICG_SWDT_CLOCK_DIV1 (0UL) /*!< SWDTCLK */
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#define ICG_SWDT_CLOCK_DIV16 (ICG_ICG0_SWDTCKS_2) /*!< SWDTCLK/16 */
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#define ICG_SWDT_CLOCK_DIV32 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/32 */
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#define ICG_SWDT_CLOCK_DIV64 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1) /*!< SWDTCLK/64 */
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#define ICG_SWDT_CLOCK_DIV128 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/128 */
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#define ICG_SWDT_CLOCK_DIV256 (ICG_ICG0_SWDTCKS_3) /*!< SWDTCLK/256 */
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#define ICG_SWDT_CLOCK_DIV2048 (ICG_ICG0_SWDTCKS_3 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/2048 */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range
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* @{
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*/
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#define ICG_SWDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
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#define ICG_SWDT_RANGE_0TO25PCT (ICG_ICG0_SWDTWDPT_0) /*!< 0%~25% */
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#define ICG_SWDT_RANGE_25TO50PCT (ICG_ICG0_SWDTWDPT_1) /*!< 25%~50% */
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#define ICG_SWDT_RANGE_0TO50PCT (ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% */
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#define ICG_SWDT_RANGE_50TO75PCT (ICG_ICG0_SWDTWDPT_2) /*!< 50%~75% */
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#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~75% */
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#define ICG_SWDT_RANGE_25TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~75% */
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#define ICG_SWDT_RANGE_0TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~75% */
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#define ICG_SWDT_RANGE_75TO100PCT (ICG_ICG0_SWDTWDPT_3) /*!< 75%~100% */
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#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 75%~100% */
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#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~50% & 75%~100% */
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#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% & 75%~100% */
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#define ICG_SWDT_RANGE_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2)) /*!< 50%~100% */
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#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~100% */
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#define ICG_SWDT_RANGE_25TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~100% */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count
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* @brief SWDT count control in the sleep/stop mode
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* @{
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*/
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#define ICG_SWDT_LPM_COUNT_CONTINUE (0UL) /*!< SWDT count continue in the sleep/stop mode */
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#define ICG_SWDT_LPM_COUNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< SWDT count stop in the sleep/stop mode */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_WDT_Reset_State ICG WDT Reset State
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* @{
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*/
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#define ICG_WDT_RESET_AUTOSTART (0UL) /*!< WDT Auto Start after reset */
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#define ICG_WDT_RESET_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_WDT_Trigger_Type ICG WDT Trigger Type
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* @{
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*/
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#define ICG_WDT_TRIG_INT (0UL) /*!< WDT trigger interrupt */
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#define ICG_WDT_TRIG_RESET (ICG_ICG0_WDTITS) /*!< WDT trigger reset */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_WDT_Counter_Cycle ICG WDT Counter Cycle
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* @{
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*/
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#define ICG_WDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
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#define ICG_WDT_COUNTER_CYCLE_4096 (ICG_ICG0_WDTPERI_0) /*!< 4096 clock cycle */
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#define ICG_WDT_COUNTER_CYCLE_16384 (ICG_ICG0_WDTPERI_1) /*!< 16384 clock cycle */
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#define ICG_WDT_COUNTER_CYCLE_65536 (ICG_ICG0_WDTPERI) /*!< 65536 clock cycle */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division
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* @{
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*/
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#define ICG_WDT_CLOCK_DIV4 (ICG_ICG0_WDTCKS_1) /*!< PCLK3/4 */
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#define ICG_WDT_CLOCK_DIV64 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/64 */
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#define ICG_WDT_CLOCK_DIV128 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/128 */
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#define ICG_WDT_CLOCK_DIV256 (ICG_ICG0_WDTCKS_3) /*!< PCLK3/256 */
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#define ICG_WDT_CLOCK_DIV512 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/512 */
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#define ICG_WDT_CLOCK_DIV1024 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/1024 */
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#define ICG_WDT_CLOCK_DIV2028 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/2048 */
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#define ICG_WDT_CLOCK_DIV8192 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/8192 */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range
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* @{
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*/
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#define ICG_WDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
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#define ICG_WDT_RANGE_0TO25PCT (ICG_ICG0_WDTWDPT_0) /*!< 0%~25% */
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#define ICG_WDT_RANGE_25TO50PCT (ICG_ICG0_WDTWDPT_1) /*!< 25%~50% */
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#define ICG_WDT_RANGE_0TO50PCT (ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% */
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#define ICG_WDT_RANGE_50TO75PCT (ICG_ICG0_WDTWDPT_2) /*!< 50%~75% */
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#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~75% */
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#define ICG_WDT_RANGE_25TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~75% */
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#define ICG_WDT_RANGE_0TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~75% */
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#define ICG_WDT_RANGE_75TO100PCT (ICG_ICG0_WDTWDPT_3) /*!< 75%~100% */
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#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 75%~100% */
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#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1) /*!< 25%~50% & 75%~100% */
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#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% & 75%~100% */
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#define ICG_WDT_RANGE_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2) /*!< 50%~100% */
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#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~100% */
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#define ICG_WDT_RANGE_25TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~100% */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count
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* @brief WDT count control in the sleep mode
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* @{
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*/
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#define ICG_WDT_LPM_COUNT_CONTINUE (0UL) /*!< WDT count continue in the sleep mode */
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#define ICG_WDT_LPM_COUNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< WDT count stop in the sleep mode */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select
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* @{
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*/
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#define ICG_HRC_FREQ_20MHZ (0UL) /*!< HRC frequency 20MHZ */
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#define ICG_HRC_FREQ_16MHZ (ICG_ICG1_HRCFREQSEL) /*!< HRC frequency 16MHZ */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_HRC_Reset_State ICG HRC Reset State
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* @{
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*/
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#define ICG_HRC_RESET_OSCILLATION (0UL) /*!< HRC Oscillation after reset */
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#define ICG_HRC_RESET_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold
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* @{
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*/
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#define ICG_BOR_VOL_THRESHOLD_1P9 (0UL) /*!< BOR voltage threshold 1.9V */
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#define ICG_BOR_VOL_THRESHOLD_2P0 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */
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#define ICG_BOR_VOL_THRESHOLD_2P1 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */
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#define ICG_BOR_VOL_THRESHOLD_2P3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_BOR_Reset_State ICG BOR Reset State
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* @{
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*/
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#define ICG_BOR_RESET_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */
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#define ICG_BOR_RESET_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_FLASH_Bank_Reset_State ICG FLASH Bank Reset State
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* @{
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*/
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#define ICG_FLASH_BANK_1 (0xFFFFFFFFUL) /*!< After reset, 1MBytes flash are provided by bank0 */
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#define ICG_FLASH_BANK_12 (0x004B4B4BUL) /*!< After reset, 1MBytes flash are provided by bank0 and bank1 with 512Bytes each */
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/**
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* @}
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*/
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/**
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* @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State
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* @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF
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* @{
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*/
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#define ICG_FLASH_PROTECT_RESET_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */
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#define ICG_FLASH_PROTECT_RESET_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @defgroup ICG_Register_Configuration ICG Register Configuration
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* @{
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*/
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/**
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*******************************************************************************
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* @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration
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* @{
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*******************************************************************************
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*/
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/* SWDT register config */
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#define ICG0_RB_SWDT_AUTS (ICG_SWDT_RESET_STOP)
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#define ICG0_RB_SWDT_ITS (ICG_SWDT_TRIG_INT)
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#define ICG0_RB_SWDT_PERI (ICG_SWDT_COUNTER_CYCLE_65536)
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#define ICG0_RB_SWDT_CKS (ICG_SWDT_CLOCK_DIV2048)
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#define ICG0_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT)
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#define ICG0_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_COUNT_CONTINUE)
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/* SWDT register value */
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#define ICG0_RB_SWDT_CONFIG (ICG0_RB_SWDT_AUTS | ICG0_RB_SWDT_ITS | \
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ICG0_RB_SWDT_PERI | ICG0_RB_SWDT_CKS | \
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ICG0_RB_SWDT_WDPT | ICG0_RB_SWDT_SLTPOFF)
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/**
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* @}
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*/
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/**
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*******************************************************************************
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* @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration
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* @{
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*******************************************************************************
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*/
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/* WDT register config */
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#define ICG0_RB_WDT_AUTS (ICG_WDT_RESET_STOP)
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#define ICG0_RB_WDT_ITS (ICG_WDT_TRIG_INT)
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#define ICG0_RB_WDT_PERI (ICG_WDT_COUNTER_CYCLE_65536)
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#define ICG0_RB_WDT_CKS (ICG_WDT_CLOCK_DIV8192)
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#define ICG0_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT)
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#define ICG0_RB_WDT_SLTPOFF (ICG_WDT_LPM_COUNT_CONTINUE)
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/* WDT register value */
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#define ICG0_RB_WDT_CONFIG (ICG0_RB_WDT_AUTS | ICG0_RB_WDT_ITS | \
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ICG0_RB_WDT_PERI | ICG0_RB_WDT_CKS | \
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ICG0_RB_WDT_WDPT | ICG0_RB_WDT_SLTPOFF)
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/**
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* @}
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*/
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/**
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*******************************************************************************
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* @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration
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* @{
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*******************************************************************************
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*/
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/* HRC register config */
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#define ICG1_RB_HRC_FREQSEL (ICG_HRC_FREQ_16MHZ)
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#define ICG1_RB_HRC_STOP (ICG_HRC_RESET_STOP)
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/* HRC register value */
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#define ICG1_RB_HRC_CONFIG (ICG1_RB_HRC_FREQSEL | ICG1_RB_HRC_STOP)
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/**
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* @}
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*/
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/**
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*******************************************************************************
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* @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration
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* @{
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*******************************************************************************
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*/
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/* BOR register config */
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#define ICG1_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_2P3)
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#define ICG1_RB_BOR_DIS (ICG_BOR_RESET_DISABLE)
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/* BOR register value */
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#define ICG1_RB_BOR_CONFIG (ICG1_RB_BOR_LEV | ICG1_RB_BOR_DIS)
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/**
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* @}
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*/
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/**
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*******************************************************************************
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* @defgroup ICG_FLASH_Bank_Preload_Configuration ICG FLASH Bank Preload Configuration
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* @{
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*******************************************************************************
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*/
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/* FLASH Bank register value */
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#define ICG2_RB_FLASH_BANK_CONFIG (ICG_FLASH_BANK_1)
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/**
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* @}
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*/
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/**
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*******************************************************************************
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* @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration
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* @{
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*******************************************************************************
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*/
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/* FLASH Read Protect register value */
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#define ICG3_RB_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RESET_DISABLE)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @defgroup ICG_Register_Value ICG Register Value
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* @{
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*/
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/* ICG register value */
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#define ICG_REG_CFG0_CONSTANT (ICG0_RB_WDT_CONFIG | ICG0_RB_SWDT_CONFIG | 0xE000E000UL)
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#define ICG_REG_CFG1_CONSTANT (ICG1_RB_BOR_CONFIG | ICG1_RB_HRC_CONFIG | 0xFFF8FEFEUL)
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#define ICG_REG_CFG2_CONSTANT (ICG2_RB_FLASH_BANK_CONFIG | 0xFF000000UL)
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#define ICG_REG_CFG3_CONSTANT (ICG3_RB_FLASH_PROTECT_CONFIG | 0xFFFF0000UL)
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/* ICG reserved value */
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#define ICG_RESERVED_CONSTANT (0xFFFFFFFFUL)
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|
|
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/**
|
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* @}
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*/
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|
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/*******************************************************************************
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* Global variable definitions ('extern')
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|
******************************************************************************/
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|
|
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/*******************************************************************************
|
|
Global function prototypes (definition in C source)
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|
******************************************************************************/
|
|
|
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#endif /* DDL_ICG_ENABLE */
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|
|
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/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
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|
|
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#ifdef __cplusplus
|
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}
|
|
#endif
|
|
|
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#endif /* __HC32F4A0_ICG_H__ */
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|
|
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/*******************************************************************************
|
|
* EOF (not truncated)
|
|
******************************************************************************/
|