440 lines
16 KiB
C
440 lines
16 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_dmc.h
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* @brief This file contains all the functions prototypes of the EXMC DMC
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* (External Memory Controller: Dynamic Memory Controller) driver library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Hongjh First version
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2020-07-14 Hongjh Merge API from EXMC_DMC_Enable/Disable to EXMC_DMC_Cmd
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_DMC_H__
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#define __HC32F4A0_DMC_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_EXMC_DMC
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* @{
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*/
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#if (DDL_DMC_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup EXMC_DMC_Global_Types Dynamic Memory Controller Global Types
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* @{
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*/
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/**
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* @brief EXMC DMC CS Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t u32AddrMask; /*!< Defines the address mask.
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This parameter can be a value of @ref EXMC_DMC_Mask_Address. */
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uint32_t u32AddrMatch; /*!< Defines the address match.
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This parameter can be a value of @ref EXMC_DMC_Match_Address. */
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uint32_t u32AddrDecodeMode; /*!< Defines the address decode mode.
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This parameter can be a value of @ref EXMC_DMC_CS_Decode_Mode. */
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} stc_exmc_dmc_cs_cfg_t;
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/**
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* @brief EXMC DMC Chip Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t u32ColumnBitsNumber; /*!< Defines the number of bits of column address.
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This parameter can be a value of @ref EXMC_DMC_Column_Bits_Number. */
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uint32_t u32RowBitsNumber; /*!< Defines the number of bits of row address.
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This parameter can be a value of @ref EXMC_DMC_Row_Bits_Number. */
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uint32_t u32AutoPrechargePin; /*!< Defines the auto-precharge pin.
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This parameter can be a value of @ref EXMC_DMC_Auto_Precharge_Pin. */
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uint32_t u32MemClkSel; /*!< Defines the memory clock selection.
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This parameter can be a value of @ref EXMC_DMC_MemClock_Selection */
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uint32_t u32CkeOutputSel; /*!< Defines the CKE output selection.
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This parameter can be a value of @ref EXMC_DMC_CKE_Output_Selection */
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uint32_t u32CkeDisablePeriod; /*!< Defines the CKE disable period.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x3F */
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uint32_t u32MemBurst; /*!< Defines the number of data accesses.
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This parameter can be a value of @ref EXMC_DMC_Memory_Burst. */
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uint32_t u32AutoRefreshChips; /*!< Defines the refresh command generation for the number of memory chips.
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This parameter can be a value of @ref EXMC_DMC_Auto_Refresh_Chips. */
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}stc_exmc_dmc_chip_cfg_t;
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/**
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* @brief EXMC DMC Timing Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t u32CASL; /*!< Defines the CAS latency in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32DQSS; /*!< Defines the DQSS in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 3 */
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uint32_t u32MRD; /*!< Defines the the mode register command time in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x7F */
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uint32_t u32RAS; /*!< Defines the RAS in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
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uint32_t u32RC; /*!< Defines the RC in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
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uint32_t u32RCD; /*!< Defines the RCD in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32RFC; /*!< Defines the RFC in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */
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uint32_t u32RP; /*!< Defines the RP in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32RRD; /*!< Defines the RRD in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
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uint32_t u32WR; /*!< Defines the WR in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32WTR; /*!< Defines the WTR in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32XP; /*!< Defines the XP in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
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uint32_t u32XSR; /*!< Defines the XSR in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
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uint32_t u32ESR; /*!< Defines the ESR in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
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} stc_exmc_dmc_timing_cfg_t;
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/**
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* @brief EXMC DMC Initialization Structure definition
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*/
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typedef struct
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{
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uint32_t u32DmcMemWidth; /*!< DMC memory width.
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This parameter can be a value of @ref EXMC_DMC_Memory_Width. */
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uint32_t u32RefreshPeriod; /*!< DMC memory refresh period.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFF */
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stc_exmc_dmc_chip_cfg_t stcChipCfg; /*!< DMC memory chip configure.
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This structure details refer @ref stc_exmc_dmc_chip_cfg_t. */
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stc_exmc_dmc_timing_cfg_t stcTimingCfg; /*!< DMC memory timing configure.
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This structure details refer @ref stc_exmc_dmc_timing_cfg_t. */
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} stc_exmc_dmc_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup EXMC_DMC_Global_Macros Dynamic Memory Controller Global Macros
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* @{
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*/
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/**
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* @defgroup EXMC_DMC_Memory_Width EXMC DMC Memory Width
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* @{
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*/
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#define EXMC_DMC_MEMORY_WIDTH_16BIT (0UL)
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#define EXMC_DMC_MEMORY_WIDTH_32BIT (DMC_BACR_DMCMW_0)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Chip EXMC DMC Chip
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* @{
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*/
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#define EXMC_DMC_CHIP_0 (0UL) /*!< Chip 0 */
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#define EXMC_DMC_CHIP_1 (1UL) /*!< Chip 1 */
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#define EXMC_DMC_CHIP_2 (2UL) /*!< Chip 2 */
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#define EXMC_DMC_CHIP_3 (3UL) /*!< Chip 3 */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Bank EXMC DMC Bank
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* @{
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*/
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#define EXMC_DMC_BANK_0 (0UL) /*!< Bank 0 */
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#define EXMC_DMC_BANK_1 (1UL) /*!< Bank 1 */
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#define EXMC_DMC_BANK_2 (2UL) /*!< Bank 2 */
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#define EXMC_DMC_BANK_3 (3UL) /*!< Bank 3 */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Current_Status EXMC DMC Current Status
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* @{
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*/
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#define EXMC_DMC_CURR_STATUS_CONFIGURE (0UL)
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#define EXMC_DMC_CURR_STATUS_READY (DMC_STSR_STATUS_0)
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#define EXMC_DMC_CURR_STATUS_PAUSED (DMC_STSR_STATUS_1)
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#define EXMC_DMC_CURR_STATUS_LOWPOWER (DMC_STSR_STATUS)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Control_State EXMC DMC Control State
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* @{
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*/
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#define EXMC_DMC_CTL_STATE_GO (0UL)
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#define EXMC_DMC_CTL_STATE_SLEEP (1UL)
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#define EXMC_DMC_CTL_STATE_WAKEUP (2UL)
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#define EXMC_DMC_CTL_STATE_PAUSE (3UL)
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#define EXMC_DMC_CTL_STATE_CONFIGURE (4UL)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Command EXMC DMC Command
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* @{
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*/
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#define EXMC_DMC_CMD_PRECHARGEALL (0UL) /*!< Precharge all */
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#define EXMC_DMC_CMD_AUTOREFRESH (DMC_CMDR_CMD_0) /*!< Auto refresh */
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#define EXMC_DMC_CMD_MDREGCONFIG (DMC_CMDR_CMD_1) /*!< Set memory device mode register */
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#define EXMC_DMC_CMD_NOP (DMC_CMDR_CMD) /*!< NOP */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Refresh_Period_Max EXMC DMC Refresh Period Max
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* @{
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*/
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#define EXMC_DMC_REFRESH_PERIOD_MAX (0x00007FFFUL)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_CS_Decode_Mode EXMC DMC CS Decode Mode
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* @{
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*/
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#define EXMC_DMC_CS_DECODE_ROWBANKCOL (0UL) /*!< Row -> Bank -> Column */
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#define EXMC_DMC_CS_DECODE_BANKROWCOL (DMC_CSCR_BRC) /*!< Bank -> Row -> Column */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Column_Bits_Number EXMC DMC Column Bits Number
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* @{
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*/
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#define EXMC_DMC_COLUMN_BITS_NUM_8 (0UL)
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#define EXMC_DMC_COLUMN_BITS_NUM_9 (DMC_CPCR_COLBS_0)
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#define EXMC_DMC_COLUMN_BITS_NUM_10 (DMC_CPCR_COLBS_1)
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#define EXMC_DMC_COLUMN_BITS_NUM_11 (DMC_CPCR_COLBS_1 | \
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DMC_CPCR_COLBS_0)
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#define EXMC_DMC_COLUMN_BITS_NUM_12 (DMC_CPCR_COLBS_2)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Row_Bits_Number EXMC DMC Row Bits Number
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* @{
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*/
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#define EXMC_DMC_ROW_BITS_NUM_11 (0UL)
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#define EXMC_DMC_ROW_BITS_NUM_12 (DMC_CPCR_ROWBS_0)
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#define EXMC_DMC_ROW_BITS_NUM_13 (DMC_CPCR_ROWBS_1)
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#define EXMC_DMC_ROW_BITS_NUM_14 (DMC_CPCR_ROWBS_1 | \
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DMC_CPCR_ROWBS_0)
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#define EXMC_DMC_ROW_BITS_NUM_15 (DMC_CPCR_ROWBS_2)
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#define EXMC_DMC_ROW_BITS_NUM_16 (DMC_CPCR_ROWBS_2 | \
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DMC_CPCR_ROWBS_0)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Auto_Precharge_Pin EXMC DMC Auto Pre-charge Pin
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* @{
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*/
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#define EXMC_DMC_AUTO_PRECHARGE_A8 (DMC_CPCR_APBS)
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#define EXMC_DMC_AUTO_PRECHARGE_A10 (0UL)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_CKE_Output_Selection EXMC DMC CKE Output Selection
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* @{
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*/
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#define EXMC_DMC_CKE_OUTPUT_ENABLE (0UL)
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#define EXMC_DMC_CKE_OUTPUT_DISABLE (DMC_CPCR_CKEDIS)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_MemClock_Selection EXMC DMC MemClock Selection
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* @{
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*/
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#define EXMC_DMC_MEMCLK_NORMAL_OUTPUT (0UL)
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#define EXMC_DMC_MEMCLK_NOP_STOP_OUTPUT (DMC_CPCR_CKSTOP)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Memory_Burst EXMC DMC Memory Burst
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* @{
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*/
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#define EXMC_DMC_MEM_BURST_1 (0UL)
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#define EXMC_DMC_MEM_BURST_2 (DMC_CPCR_BURST_0)
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#define EXMC_DMC_MEM_BURST_4 (DMC_CPCR_BURST_1)
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#define EXMC_DMC_MEM_BURST_8 (DMC_CPCR_BURST_1 | \
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DMC_CPCR_BURST_0)
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#define EXMC_DMC_MEM_BURST_16 (DMC_CPCR_BURST_2)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Auto_Refresh_Chips EXMC DMC Auto Refresh
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* @{
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*/
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#define EXMC_DMC_AUTO_REFRESH_CHIP_0 (0UL)
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#define EXMC_DMC_AUTO_REFRESH_CHIPS_01 (DMC_CPCR_ACTCP_0)
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#define EXMC_DMC_AUTO_REFRESH_CHIPS_012 (DMC_CPCR_ACTCP_1)
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#define EXMC_DMC_AUTO_REFRESH_CHIPS_0123 (DMC_CPCR_ACTCP)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Match_Address EXMC DMC Match Address
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* @{
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*/
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#define EXMC_DMC_ADDR_MATCH_0X80000000 (0x80UL << DMC_CSCR_ADDMAT_POS)
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#define EXMC_DMC_ADDR_MATCH_0X81000000 (0x81UL << DMC_CSCR_ADDMAT_POS)
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#define EXMC_DMC_ADDR_MATCH_0X82000000 (0x82UL << DMC_CSCR_ADDMAT_POS)
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#define EXMC_DMC_ADDR_MATCH_0X83000000 (0x83UL << DMC_CSCR_ADDMAT_POS)
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#define EXMC_DMC_ADDR_MATCH_0X84000000 (0x84UL << DMC_CSCR_ADDMAT_POS)
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#define EXMC_DMC_ADDR_MATCH_0X85000000 (0x85UL << DMC_CSCR_ADDMAT_POS)
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#define EXMC_DMC_ADDR_MATCH_0X86000000 (0x86UL << DMC_CSCR_ADDMAT_POS)
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#define EXMC_DMC_ADDR_MATCH_0X87000000 (0x87UL << DMC_CSCR_ADDMAT_POS)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_DMC_Mask_Address EXMC DMC Mask Address
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* @{
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*/
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#define EXMC_DMC_ADDR_MASK_16MB (0xFFUL)
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#define EXMC_DMC_ADDR_MASK_32MB (0xFEUL)
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#define EXMC_DMC_ADDR_MASK_64MB (0xFCUL)
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#define EXMC_DMC_ADDR_MASK_128MB (0xF8UL)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup EXMC_DMC_Global_Functions
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* @{
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*/
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/**
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* @brief Get DMC status.
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* @param None
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* @retval Returned value can be one of the following values:
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* @arg EXMC_DMC_CURR_STATUS_CONFIGURE: Configure status
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* @arg EXMC_DMC_CURR_STATUS_READY: Ready status
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* @arg EXMC_DMC_CURR_STATUS_PAUSED: Pause status
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* @arg EXMC_DMC_CURR_STATUS_LOWPOWER: Sleep for low power status
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*/
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__STATIC_INLINE uint32_t EXMC_DMC_GetStatus(void)
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{
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return READ_REG32_BIT(M4_DMC->STSR, DMC_STSR_STATUS);
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}
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/* Initialization and configuration EXMC DMC functions */
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en_result_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcInit);
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void EXMC_DMC_DeInit(void);
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en_result_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcInit);
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void EXMC_DMC_Cmd(en_functional_state_t enNewState);
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en_result_t EXMC_DMC_CsConfig(uint32_t u32Chip,
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const stc_exmc_dmc_cs_cfg_t *pstcCfg);
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uint32_t EXMC_DMC_ChipStartAddress(uint32_t u32Chip);
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uint32_t EXMC_DMC_ChipEndAddress(uint32_t u32Chip);
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en_result_t EXMC_DMC_SetCommand(uint32_t u32Chip,
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uint32_t u32Bank,
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uint32_t u32Cmd,
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uint32_t u32Address);
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void EXMC_DMC_SetState(uint32_t u32State);
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/**
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* @}
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*/
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#endif /* DDL_DMC_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_DMC_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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