197 lines
6.1 KiB
C
197 lines
6.1 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 SummerGift first version
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* 2019-04-09 WillianChan add stm32f469-st-disco bsp
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* 2020-06-20 thread-liu add stm32mp157-dk1 bsp
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*/
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#include "board.h"
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void PeriphCommonClock_Config(void);
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/**Configure LSE Drive Capability
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE
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|RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIG;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1;
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/**PLL1 Config
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*/
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 3;
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RCC_OscInitStruct.PLL.PLLN = 81;
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RCC_OscInitStruct.PLL.PLLP = 1;
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RCC_OscInitStruct.PLL.PLLQ = 1;
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RCC_OscInitStruct.PLL.PLLR = 1;
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RCC_OscInitStruct.PLL.PLLFRACV = 0x800;
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RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
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RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
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RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
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/**PLL2 Config
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*/
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RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE;
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RCC_OscInitStruct.PLL2.PLLM = 3;
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RCC_OscInitStruct.PLL2.PLLN = 66;
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RCC_OscInitStruct.PLL2.PLLP = 2;
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RCC_OscInitStruct.PLL2.PLLQ = 1;
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RCC_OscInitStruct.PLL2.PLLR = 1;
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RCC_OscInitStruct.PLL2.PLLFRACV = 0x1400;
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RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
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RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
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RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
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/**PLL3 Config
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*/
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RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE;
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RCC_OscInitStruct.PLL3.PLLM = 2;
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RCC_OscInitStruct.PLL3.PLLN = 34;
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RCC_OscInitStruct.PLL3.PLLP = 2;
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RCC_OscInitStruct.PLL3.PLLQ = 17;
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RCC_OscInitStruct.PLL3.PLLR = 37;
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RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1;
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RCC_OscInitStruct.PLL3.PLLFRACV = 0x1A04;
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RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
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RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
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RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
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/**PLL4 Config
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*/
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RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE;
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RCC_OscInitStruct.PLL4.PLLM = 4;
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RCC_OscInitStruct.PLL4.PLLN = 99;
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RCC_OscInitStruct.PLL4.PLLP = 6;
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RCC_OscInitStruct.PLL4.PLLQ = 8;
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RCC_OscInitStruct.PLL4.PLLR = 8;
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RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0;
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RCC_OscInitStruct.PLL4.PLLFRACV = 0;
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RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
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RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
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RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**RCC Clock Config
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
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|RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4
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|RCC_CLOCKTYPE_PCLK5|RCC_CLOCKTYPE_MPU;
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RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1;
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RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2;
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RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2;
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RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1;
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RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3;
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RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1;
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RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2;
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RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4;
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RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Set the HSE division factor for RTC clock
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*/
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__HAL_RCC_RTC_HSEDIV(24);
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/* Configure the peripherals common clocks */
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if(IS_ENGINEERING_BOOT_MODE())
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{
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PeriphCommonClock_Config();
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}
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}
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/**
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* @brief Peripherals Common Clock Configuration
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* @retval None
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*/
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void PeriphCommonClock_Config(void) {
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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/** Initializes the common periph clock
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*/
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER;
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PeriphClkInit.CkperClockSelection = RCC_CKPERCLKSOURCE_HSE;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
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Error_Handler();
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}
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}
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extern void rt_hw_systick_init(void);
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extern int rt_hw_usart_init(void);
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void rt_hw_board_init()
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{
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/* HAL_Init() function is called at the beginning of the program */
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HAL_Init();
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/* enable interrupt */
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__set_PRIMASK(0);
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/* Configure the system clock */
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if (IS_ENGINEERING_BOOT_MODE()) {
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/* Configure the system clock */
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SystemClock_Config();
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}
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/* disable interrupt */
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__set_PRIMASK(1);
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rt_hw_systick_init();
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/* Heap initialization */
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#if defined(RT_USING_HEAP)
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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/* Pin driver initialization is open by default */
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#ifdef RT_USING_PIN
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rt_hw_pin_init();
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#endif
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/* USART driver initialization is open by default */
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#ifdef RT_USING_SERIAL
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rt_hw_usart_init();
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#endif
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/* Set the shell console output device */
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* Board underlying hardware initialization */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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