1061 lines
33 KiB
C
1061 lines
33 KiB
C
/******************************************************************************
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**
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** \file gh_uart1.c
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**
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** \brief UART1.
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**
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** Copyright: 2012 - 2016 (C) GoKe Microelectronics
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \note Do not modify this file as it is generated automatically.
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**
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******************************************************************************/
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#ifndef SRC_INLINE
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#include "gh_uart1.h"
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#endif
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/*----------------------------------------------------------------------------*/
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/* registers */
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/*----------------------------------------------------------------------------*/
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#define REG_UART1_RBR_REAL FIO_ADDRESS(UART1,0x7001F000) /* read */
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#define REG_UART1_THR_REAL FIO_ADDRESS(UART1,0x7001F000) /* write */
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#define REG_UART1_DLL_REAL FIO_ADDRESS(UART1,0x7001F000) /* read/write */
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#define REG_UART1_IER_REAL FIO_ADDRESS(UART1,0x7001F004) /* read/write */
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#define REG_UART1_DLH_REAL FIO_ADDRESS(UART1,0x7001F004) /* read/write */
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#define REG_UART1_IIR_REAL FIO_ADDRESS(UART1,0x7001F008) /* read */
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#define REG_UART1_FCR_REAL FIO_ADDRESS(UART1,0x7001F008) /* write */
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#define REG_UART1_LCR_REAL FIO_ADDRESS(UART1,0x7001F00C) /* read/write */
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#define REG_UART1_MCR_REAL FIO_ADDRESS(UART1,0x7001F010) /* read/write */
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#define REG_UART1_LSR_REAL FIO_ADDRESS(UART1,0x7001F014) /* read */
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#define REG_UART1_MSR_REAL FIO_ADDRESS(UART1,0x7001F018) /* read */
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#define REG_UART1_SCR_REAL FIO_ADDRESS(UART1,0x7001F01C) /* read/write */
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/*----------------------------------------------------------------------------*/
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/* bit group structures */
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/*----------------------------------------------------------------------------*/
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typedef union { /* UART1_RBR */
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U32 all;
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struct {
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U32 data : 8;
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U32 : 24;
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} bitc;
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} GH_UART1_RBR_REAL_S;
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typedef union { /* UART1_THR */
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U32 all;
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struct {
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U32 data : 8;
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U32 : 24;
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} bitc;
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} GH_UART1_THR_REAL_S;
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typedef union { /* UART1_DLL */
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U32 all;
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struct {
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U32 bauddivint_l : 8;
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U32 : 24;
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} bitc;
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} GH_UART1_DLL_REAL_S;
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typedef union { /* UART1_IER */
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U32 all;
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struct {
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U32 erbfi : 1;
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U32 etbei : 1;
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U32 elsi : 1;
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U32 edssi : 1;
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U32 : 28;
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} bitc;
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} GH_UART1_IER_REAL_S;
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typedef union { /* UART1_DLH */
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U32 all;
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struct {
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U32 bauddivint_h : 8;
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U32 : 24;
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} bitc;
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} GH_UART1_DLH_REAL_S;
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typedef union { /* UART1_IIR */
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U32 all;
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struct {
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U32 interrupt_id : 4;
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U32 : 2;
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U32 fifos_enabled : 2;
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U32 : 24;
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} bitc;
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} GH_UART1_IIR_REAL_S;
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typedef union { /* UART1_FCR */
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U32 all;
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struct {
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U32 fifo_enable : 1;
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U32 rcvr_fifo_reset : 1;
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U32 xmit_fifo_reset : 1;
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U32 dma_mode : 1;
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U32 tx_empty_trigger : 2;
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U32 rcvr_trigger : 2;
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U32 : 24;
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} bitc;
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} GH_UART1_FCR_REAL_S;
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typedef union { /* UART1_LCR */
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U32 all;
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struct {
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U32 cls : 2;
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U32 stop : 1;
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U32 pen : 1;
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U32 eps : 1;
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U32 sticky_parity : 1;
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U32 breaks : 1;
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U32 dlab : 1;
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U32 : 24;
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} bitc;
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} GH_UART1_LCR_REAL_S;
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typedef union { /* UART1_MCR */
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U32 all;
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struct {
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U32 dtr : 1;
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U32 rts : 1;
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U32 out1 : 1;
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U32 out2 : 1;
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U32 loopback : 1;
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U32 afce : 1;
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U32 sire : 1;
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U32 : 25;
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} bitc;
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} GH_UART1_MCR_REAL_S;
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typedef union { /* UART1_LSR */
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U32 all;
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struct {
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U32 dr : 1;
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U32 oe : 1;
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U32 pe : 1;
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U32 fe : 1;
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U32 bi : 1;
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U32 : 1;
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U32 temt : 1;
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U32 : 25;
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} bitc;
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} GH_UART1_LSR_REAL_S;
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typedef union { /* UART1_MSR */
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U32 all;
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struct {
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U32 dcts : 1;
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U32 ddsr : 1;
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U32 teri : 1;
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U32 ddcd : 1;
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U32 cts : 1;
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U32 dsr : 1;
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U32 ri : 1;
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U32 dcd : 1;
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U32 : 24;
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} bitc;
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} GH_UART1_MSR_REAL_S;
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typedef union { /* UART1_SCR */
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U32 all;
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struct {
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U32 scr : 8;
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U32 : 24;
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} bitc;
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} GH_UART1_SCR_REAL_S;
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/*----------------------------------------------------------------------------*/
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/* mirror variables */
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/*----------------------------------------------------------------------------*/
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GH_UART1_THR_S m_uart1_thr;
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GH_UART1_FCR_S m_uart1_fcr;
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/*----------------------------------------------------------------------------*/
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/* register UART1_RBR (read) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE U32 GH_UART1_get_RBR(void)
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{
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GH_UART1_RBR_REAL_S real;
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GH_UART1_RBR_S dummy;
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dummy.all = 0;
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real.all = (*(volatile U32 *)REG_UART1_RBR_REAL);
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dummy.bitc.data = real.bitc.data;
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return dummy.all;
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}
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GH_INLINE U8 GH_UART1_get_RBR_Data(void)
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{
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GH_UART1_RBR_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_RBR_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.data;
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}
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/*----------------------------------------------------------------------------*/
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/* register UART1_THR (write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_UART1_set_THR(U32 data)
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{
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m_uart1_thr.all = data;
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GH_UART1_THR_REAL_S real;
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GH_UART1_THR_S dummy;
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dummy.all = data ;
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real.bitc.data = dummy.bitc.data;
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*(volatile U32 *)REG_UART1_THR_REAL = real.all;
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}
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GH_INLINE U32 GH_UART1_getm_THR(void)
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{
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#if GH_UART1_ENABLE_DEBUG_PRINT
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GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_THR] --> 0x%08x\n",
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m_uart1_thr.all);
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#endif
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return m_uart1_thr.all;
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}
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GH_INLINE void GH_UART1_set_THR_Data(U8 data)
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{
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m_uart1_thr.bitc.data = data;
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GH_UART1_THR_REAL_S real;
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real.bitc.data = m_uart1_thr.bitc.data;
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*(volatile U32 *)REG_UART1_THR_REAL = real.all;
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}
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GH_INLINE U8 GH_UART1_getm_THR_Data(void)
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{
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#if GH_UART1_ENABLE_DEBUG_PRINT
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GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_THR_Data] --> 0x%08x\n",
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m_uart1_thr.bitc.data);
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#endif
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return m_uart1_thr.bitc.data;
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}
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/*----------------------------------------------------------------------------*/
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/* register UART1_DLL (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_UART1_set_DLL(U32 data)
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{
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GH_UART1_DLL_REAL_S real;
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GH_UART1_DLL_S dummy;
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dummy.all = data ;
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real.bitc.bauddivint_l = dummy.bitc.bauddivint_l;
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*(volatile U32 *)REG_UART1_DLL_REAL = real.all;
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}
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GH_INLINE U32 GH_UART1_get_DLL(void)
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{
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GH_UART1_DLL_REAL_S real;
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GH_UART1_DLL_S dummy;
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dummy.all = 0;
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real.all = (*(volatile U32 *)REG_UART1_DLL_REAL);
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dummy.bitc.bauddivint_l = real.bitc.bauddivint_l;
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return dummy.all;
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}
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GH_INLINE void GH_UART1_set_DLL_BaudDivint_L(U8 data)
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{
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GH_UART1_DLL_REAL_S d;
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d.all = *(volatile U32 *)REG_UART1_DLL_REAL;
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d.bitc.bauddivint_l = data;
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*(volatile U32 *)REG_UART1_DLL_REAL = d.all;
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}
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GH_INLINE U8 GH_UART1_get_DLL_BaudDivint_L(void)
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{
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GH_UART1_DLL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_DLL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.bauddivint_l;
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}
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/*----------------------------------------------------------------------------*/
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/* register UART1_IER (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_UART1_set_IER(U32 data)
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{
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GH_UART1_IER_REAL_S real;
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GH_UART1_IER_S dummy;
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dummy.all = data ;
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real.bitc.erbfi = dummy.bitc.erbfi;
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real.bitc.etbei = dummy.bitc.etbei;
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real.bitc.elsi = dummy.bitc.elsi;
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real.bitc.edssi = dummy.bitc.edssi;
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*(volatile U32 *)REG_UART1_IER_REAL = real.all;
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}
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GH_INLINE U32 GH_UART1_get_IER(void)
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{
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GH_UART1_IER_REAL_S real;
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GH_UART1_IER_S dummy;
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dummy.all = 0;
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real.all = (*(volatile U32 *)REG_UART1_IER_REAL);
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dummy.bitc.erbfi = real.bitc.erbfi;
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dummy.bitc.etbei = real.bitc.etbei;
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dummy.bitc.elsi = real.bitc.elsi;
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dummy.bitc.edssi = real.bitc.edssi;
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return dummy.all;
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}
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GH_INLINE void GH_UART1_set_IER_erbfi(U8 data)
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{
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GH_UART1_IER_REAL_S d;
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d.all = *(volatile U32 *)REG_UART1_IER_REAL;
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d.bitc.erbfi = data;
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*(volatile U32 *)REG_UART1_IER_REAL = d.all;
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}
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GH_INLINE U8 GH_UART1_get_IER_erbfi(void)
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{
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GH_UART1_IER_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_IER_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.erbfi;
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}
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GH_INLINE void GH_UART1_set_IER_etbei(U8 data)
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{
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GH_UART1_IER_REAL_S d;
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d.all = *(volatile U32 *)REG_UART1_IER_REAL;
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d.bitc.etbei = data;
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*(volatile U32 *)REG_UART1_IER_REAL = d.all;
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}
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GH_INLINE U8 GH_UART1_get_IER_etbei(void)
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{
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GH_UART1_IER_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_IER_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.etbei;
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}
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GH_INLINE void GH_UART1_set_IER_elsi(U8 data)
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{
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GH_UART1_IER_REAL_S d;
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d.all = *(volatile U32 *)REG_UART1_IER_REAL;
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d.bitc.elsi = data;
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*(volatile U32 *)REG_UART1_IER_REAL = d.all;
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}
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GH_INLINE U8 GH_UART1_get_IER_elsi(void)
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{
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GH_UART1_IER_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_IER_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.elsi;
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}
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GH_INLINE void GH_UART1_set_IER_edssi(U8 data)
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{
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GH_UART1_IER_REAL_S d;
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d.all = *(volatile U32 *)REG_UART1_IER_REAL;
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d.bitc.edssi = data;
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*(volatile U32 *)REG_UART1_IER_REAL = d.all;
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}
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GH_INLINE U8 GH_UART1_get_IER_edssi(void)
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{
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GH_UART1_IER_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_IER_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.edssi;
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}
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/*----------------------------------------------------------------------------*/
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/* register UART1_DLH (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_UART1_set_DLH(U32 data)
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{
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GH_UART1_DLH_REAL_S real;
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GH_UART1_DLH_S dummy;
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dummy.all = data ;
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real.bitc.bauddivint_h = dummy.bitc.bauddivint_h;
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*(volatile U32 *)REG_UART1_DLH_REAL = real.all;
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}
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GH_INLINE U32 GH_UART1_get_DLH(void)
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{
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GH_UART1_DLH_REAL_S real;
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GH_UART1_DLH_S dummy;
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dummy.all = 0;
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real.all = (*(volatile U32 *)REG_UART1_DLH_REAL);
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dummy.bitc.bauddivint_h = real.bitc.bauddivint_h;
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return dummy.all;
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}
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GH_INLINE void GH_UART1_set_DLH_BaudDivint_H(U8 data)
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{
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GH_UART1_DLH_REAL_S d;
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d.all = *(volatile U32 *)REG_UART1_DLH_REAL;
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d.bitc.bauddivint_h = data;
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*(volatile U32 *)REG_UART1_DLH_REAL = d.all;
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}
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GH_INLINE U8 GH_UART1_get_DLH_BaudDivint_H(void)
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{
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GH_UART1_DLH_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_DLH_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.bauddivint_h;
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}
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/*----------------------------------------------------------------------------*/
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/* register UART1_IIR (read) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE U32 GH_UART1_get_IIR(void)
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{
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GH_UART1_IIR_REAL_S real;
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GH_UART1_IIR_S dummy;
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dummy.all = 0;
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real.all = (*(volatile U32 *)REG_UART1_IIR_REAL);
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dummy.bitc.interrupt_id = real.bitc.interrupt_id;
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dummy.bitc.fifos_enabled = real.bitc.fifos_enabled;
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return dummy.all;
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}
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GH_INLINE U8 GH_UART1_get_IIR_interrupt_id(void)
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{
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GH_UART1_IIR_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_IIR_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.interrupt_id;
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}
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GH_INLINE U8 GH_UART1_get_IIR_fifos_enabled(void)
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{
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GH_UART1_IIR_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_UART1_IIR_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.fifos_enabled;
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}
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/*----------------------------------------------------------------------------*/
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/* register UART1_FCR (write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_UART1_set_FCR(U32 data)
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{
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m_uart1_fcr.all = data;
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GH_UART1_FCR_REAL_S real;
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GH_UART1_FCR_S dummy;
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dummy.all = data ;
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real.bitc.fifo_enable = dummy.bitc.fifo_enable;
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real.bitc.rcvr_fifo_reset = dummy.bitc.rcvr_fifo_reset;
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real.bitc.xmit_fifo_reset = dummy.bitc.xmit_fifo_reset;
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real.bitc.dma_mode = dummy.bitc.dma_mode;
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real.bitc.tx_empty_trigger = dummy.bitc.tx_empty_trigger;
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real.bitc.rcvr_trigger = dummy.bitc.rcvr_trigger;
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*(volatile U32 *)REG_UART1_FCR_REAL = real.all;
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}
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GH_INLINE U32 GH_UART1_getm_FCR(void)
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{
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#if GH_UART1_ENABLE_DEBUG_PRINT
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GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_FCR] --> 0x%08x\n",
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m_uart1_fcr.all);
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#endif
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return m_uart1_fcr.all;
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}
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GH_INLINE void GH_UART1_set_FCR_FIFO_Enable(U8 data)
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{
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m_uart1_fcr.bitc.fifo_enable = data;
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GH_UART1_FCR_REAL_S real;
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real.bitc.fifo_enable = m_uart1_fcr.bitc.fifo_enable;
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real.bitc.rcvr_fifo_reset = m_uart1_fcr.bitc.rcvr_fifo_reset;
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real.bitc.xmit_fifo_reset = m_uart1_fcr.bitc.xmit_fifo_reset;
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real.bitc.dma_mode = m_uart1_fcr.bitc.dma_mode;
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real.bitc.tx_empty_trigger = m_uart1_fcr.bitc.tx_empty_trigger;
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real.bitc.rcvr_trigger = m_uart1_fcr.bitc.rcvr_trigger;
|
|
*(volatile U32 *)REG_UART1_FCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_getm_FCR_FIFO_Enable(void)
|
|
{
|
|
#if GH_UART1_ENABLE_DEBUG_PRINT
|
|
GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_FCR_FIFO_Enable] --> 0x%08x\n",
|
|
m_uart1_fcr.bitc.fifo_enable);
|
|
#endif
|
|
return m_uart1_fcr.bitc.fifo_enable;
|
|
}
|
|
GH_INLINE void GH_UART1_set_FCR_RCVR_FIFO_Reset(U8 data)
|
|
{
|
|
m_uart1_fcr.bitc.rcvr_fifo_reset = data;
|
|
GH_UART1_FCR_REAL_S real;
|
|
real.bitc.fifo_enable = m_uart1_fcr.bitc.fifo_enable;
|
|
real.bitc.rcvr_fifo_reset = m_uart1_fcr.bitc.rcvr_fifo_reset;
|
|
real.bitc.xmit_fifo_reset = m_uart1_fcr.bitc.xmit_fifo_reset;
|
|
real.bitc.dma_mode = m_uart1_fcr.bitc.dma_mode;
|
|
real.bitc.tx_empty_trigger = m_uart1_fcr.bitc.tx_empty_trigger;
|
|
real.bitc.rcvr_trigger = m_uart1_fcr.bitc.rcvr_trigger;
|
|
*(volatile U32 *)REG_UART1_FCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_getm_FCR_RCVR_FIFO_Reset(void)
|
|
{
|
|
#if GH_UART1_ENABLE_DEBUG_PRINT
|
|
GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_FCR_RCVR_FIFO_Reset] --> 0x%08x\n",
|
|
m_uart1_fcr.bitc.rcvr_fifo_reset);
|
|
#endif
|
|
return m_uart1_fcr.bitc.rcvr_fifo_reset;
|
|
}
|
|
GH_INLINE void GH_UART1_set_FCR_XMIT_FIFO_Reset(U8 data)
|
|
{
|
|
m_uart1_fcr.bitc.xmit_fifo_reset = data;
|
|
GH_UART1_FCR_REAL_S real;
|
|
real.bitc.fifo_enable = m_uart1_fcr.bitc.fifo_enable;
|
|
real.bitc.rcvr_fifo_reset = m_uart1_fcr.bitc.rcvr_fifo_reset;
|
|
real.bitc.xmit_fifo_reset = m_uart1_fcr.bitc.xmit_fifo_reset;
|
|
real.bitc.dma_mode = m_uart1_fcr.bitc.dma_mode;
|
|
real.bitc.tx_empty_trigger = m_uart1_fcr.bitc.tx_empty_trigger;
|
|
real.bitc.rcvr_trigger = m_uart1_fcr.bitc.rcvr_trigger;
|
|
*(volatile U32 *)REG_UART1_FCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_getm_FCR_XMIT_FIFO_Reset(void)
|
|
{
|
|
#if GH_UART1_ENABLE_DEBUG_PRINT
|
|
GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_FCR_XMIT_FIFO_Reset] --> 0x%08x\n",
|
|
m_uart1_fcr.bitc.xmit_fifo_reset);
|
|
#endif
|
|
return m_uart1_fcr.bitc.xmit_fifo_reset;
|
|
}
|
|
GH_INLINE void GH_UART1_set_FCR_DMA_Mode(U8 data)
|
|
{
|
|
m_uart1_fcr.bitc.dma_mode = data;
|
|
GH_UART1_FCR_REAL_S real;
|
|
real.bitc.fifo_enable = m_uart1_fcr.bitc.fifo_enable;
|
|
real.bitc.rcvr_fifo_reset = m_uart1_fcr.bitc.rcvr_fifo_reset;
|
|
real.bitc.xmit_fifo_reset = m_uart1_fcr.bitc.xmit_fifo_reset;
|
|
real.bitc.dma_mode = m_uart1_fcr.bitc.dma_mode;
|
|
real.bitc.tx_empty_trigger = m_uart1_fcr.bitc.tx_empty_trigger;
|
|
real.bitc.rcvr_trigger = m_uart1_fcr.bitc.rcvr_trigger;
|
|
*(volatile U32 *)REG_UART1_FCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_getm_FCR_DMA_Mode(void)
|
|
{
|
|
#if GH_UART1_ENABLE_DEBUG_PRINT
|
|
GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_FCR_DMA_Mode] --> 0x%08x\n",
|
|
m_uart1_fcr.bitc.dma_mode);
|
|
#endif
|
|
return m_uart1_fcr.bitc.dma_mode;
|
|
}
|
|
GH_INLINE void GH_UART1_set_FCR_TX_Empty_Trigger(U8 data)
|
|
{
|
|
m_uart1_fcr.bitc.tx_empty_trigger = data;
|
|
GH_UART1_FCR_REAL_S real;
|
|
real.bitc.fifo_enable = m_uart1_fcr.bitc.fifo_enable;
|
|
real.bitc.rcvr_fifo_reset = m_uart1_fcr.bitc.rcvr_fifo_reset;
|
|
real.bitc.xmit_fifo_reset = m_uart1_fcr.bitc.xmit_fifo_reset;
|
|
real.bitc.dma_mode = m_uart1_fcr.bitc.dma_mode;
|
|
real.bitc.tx_empty_trigger = m_uart1_fcr.bitc.tx_empty_trigger;
|
|
real.bitc.rcvr_trigger = m_uart1_fcr.bitc.rcvr_trigger;
|
|
*(volatile U32 *)REG_UART1_FCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_getm_FCR_TX_Empty_Trigger(void)
|
|
{
|
|
#if GH_UART1_ENABLE_DEBUG_PRINT
|
|
GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_FCR_TX_Empty_Trigger] --> 0x%08x\n",
|
|
m_uart1_fcr.bitc.tx_empty_trigger);
|
|
#endif
|
|
return m_uart1_fcr.bitc.tx_empty_trigger;
|
|
}
|
|
GH_INLINE void GH_UART1_set_FCR_RCVR_Trigger(U8 data)
|
|
{
|
|
m_uart1_fcr.bitc.rcvr_trigger = data;
|
|
GH_UART1_FCR_REAL_S real;
|
|
real.bitc.fifo_enable = m_uart1_fcr.bitc.fifo_enable;
|
|
real.bitc.rcvr_fifo_reset = m_uart1_fcr.bitc.rcvr_fifo_reset;
|
|
real.bitc.xmit_fifo_reset = m_uart1_fcr.bitc.xmit_fifo_reset;
|
|
real.bitc.dma_mode = m_uart1_fcr.bitc.dma_mode;
|
|
real.bitc.tx_empty_trigger = m_uart1_fcr.bitc.tx_empty_trigger;
|
|
real.bitc.rcvr_trigger = m_uart1_fcr.bitc.rcvr_trigger;
|
|
*(volatile U32 *)REG_UART1_FCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_getm_FCR_RCVR_Trigger(void)
|
|
{
|
|
#if GH_UART1_ENABLE_DEBUG_PRINT
|
|
GH_UART1_DEBUG_PRINT_FUNCTION( "[GH_UART1_getm_FCR_RCVR_Trigger] --> 0x%08x\n",
|
|
m_uart1_fcr.bitc.rcvr_trigger);
|
|
#endif
|
|
return m_uart1_fcr.bitc.rcvr_trigger;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register UART1_LCR (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
GH_INLINE void GH_UART1_set_LCR(U32 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S real;
|
|
GH_UART1_LCR_S dummy;
|
|
dummy.all = data ;
|
|
real.bitc.cls = dummy.bitc.cls;
|
|
real.bitc.stop = dummy.bitc.stop;
|
|
real.bitc.pen = dummy.bitc.pen;
|
|
real.bitc.eps = dummy.bitc.eps;
|
|
real.bitc.sticky_parity = dummy.bitc.sticky_parity;
|
|
real.bitc.breaks = dummy.bitc.breaks;
|
|
real.bitc.dlab = dummy.bitc.dlab;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U32 GH_UART1_get_LCR(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S real;
|
|
GH_UART1_LCR_S dummy;
|
|
dummy.all = 0;
|
|
real.all = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
dummy.bitc.cls = real.bitc.cls;
|
|
dummy.bitc.stop = real.bitc.stop;
|
|
dummy.bitc.pen = real.bitc.pen;
|
|
dummy.bitc.eps = real.bitc.eps;
|
|
dummy.bitc.sticky_parity = real.bitc.sticky_parity;
|
|
dummy.bitc.breaks = real.bitc.breaks;
|
|
dummy.bitc.dlab = real.bitc.dlab;
|
|
return dummy.all;
|
|
}
|
|
GH_INLINE void GH_UART1_set_LCR_cls(U8 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_LCR_REAL;
|
|
d.bitc.cls = data;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LCR_cls(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.cls;
|
|
}
|
|
GH_INLINE void GH_UART1_set_LCR_stop(U8 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_LCR_REAL;
|
|
d.bitc.stop = data;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LCR_stop(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.stop;
|
|
}
|
|
GH_INLINE void GH_UART1_set_LCR_pen(U8 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_LCR_REAL;
|
|
d.bitc.pen = data;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LCR_pen(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.pen;
|
|
}
|
|
GH_INLINE void GH_UART1_set_LCR_eps(U8 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_LCR_REAL;
|
|
d.bitc.eps = data;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LCR_eps(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.eps;
|
|
}
|
|
GH_INLINE void GH_UART1_set_LCR_sticky_parity(U8 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_LCR_REAL;
|
|
d.bitc.sticky_parity = data;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LCR_sticky_parity(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.sticky_parity;
|
|
}
|
|
GH_INLINE void GH_UART1_set_LCR_breaks(U8 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_LCR_REAL;
|
|
d.bitc.breaks = data;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LCR_breaks(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.breaks;
|
|
}
|
|
GH_INLINE void GH_UART1_set_LCR_dlab(U8 data)
|
|
{
|
|
GH_UART1_LCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_LCR_REAL;
|
|
d.bitc.dlab = data;
|
|
*(volatile U32 *)REG_UART1_LCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LCR_dlab(void)
|
|
{
|
|
GH_UART1_LCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.dlab;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register UART1_MCR (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
GH_INLINE void GH_UART1_set_MCR(U32 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S real;
|
|
GH_UART1_MCR_S dummy;
|
|
dummy.all = data ;
|
|
real.bitc.dtr = dummy.bitc.dtr;
|
|
real.bitc.rts = dummy.bitc.rts;
|
|
real.bitc.out1 = dummy.bitc.out1;
|
|
real.bitc.out2 = dummy.bitc.out2;
|
|
real.bitc.loopback = dummy.bitc.loopback;
|
|
real.bitc.afce = dummy.bitc.afce;
|
|
real.bitc.sire = dummy.bitc.sire;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U32 GH_UART1_get_MCR(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S real;
|
|
GH_UART1_MCR_S dummy;
|
|
dummy.all = 0;
|
|
real.all = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
dummy.bitc.dtr = real.bitc.dtr;
|
|
dummy.bitc.rts = real.bitc.rts;
|
|
dummy.bitc.out1 = real.bitc.out1;
|
|
dummy.bitc.out2 = real.bitc.out2;
|
|
dummy.bitc.loopback = real.bitc.loopback;
|
|
dummy.bitc.afce = real.bitc.afce;
|
|
dummy.bitc.sire = real.bitc.sire;
|
|
return dummy.all;
|
|
}
|
|
GH_INLINE void GH_UART1_set_MCR_dtr(U8 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_MCR_REAL;
|
|
d.bitc.dtr = data;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MCR_dtr(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.dtr;
|
|
}
|
|
GH_INLINE void GH_UART1_set_MCR_rts(U8 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_MCR_REAL;
|
|
d.bitc.rts = data;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MCR_rts(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.rts;
|
|
}
|
|
GH_INLINE void GH_UART1_set_MCR_out1(U8 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_MCR_REAL;
|
|
d.bitc.out1 = data;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MCR_out1(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.out1;
|
|
}
|
|
GH_INLINE void GH_UART1_set_MCR_out2(U8 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_MCR_REAL;
|
|
d.bitc.out2 = data;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MCR_out2(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.out2;
|
|
}
|
|
GH_INLINE void GH_UART1_set_MCR_loopback(U8 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_MCR_REAL;
|
|
d.bitc.loopback = data;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MCR_loopback(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.loopback;
|
|
}
|
|
GH_INLINE void GH_UART1_set_MCR_afce(U8 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_MCR_REAL;
|
|
d.bitc.afce = data;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MCR_afce(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.afce;
|
|
}
|
|
GH_INLINE void GH_UART1_set_MCR_sire(U8 data)
|
|
{
|
|
GH_UART1_MCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_MCR_REAL;
|
|
d.bitc.sire = data;
|
|
*(volatile U32 *)REG_UART1_MCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MCR_sire(void)
|
|
{
|
|
GH_UART1_MCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.sire;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register UART1_LSR (read) */
|
|
/*----------------------------------------------------------------------------*/
|
|
GH_INLINE U32 GH_UART1_get_LSR(void)
|
|
{
|
|
GH_UART1_LSR_REAL_S real;
|
|
GH_UART1_LSR_S dummy;
|
|
dummy.all = 0;
|
|
real.all = (*(volatile U32 *)REG_UART1_LSR_REAL);
|
|
|
|
dummy.bitc.dr = real.bitc.dr;
|
|
dummy.bitc.oe = real.bitc.oe;
|
|
dummy.bitc.pe = real.bitc.pe;
|
|
dummy.bitc.fe = real.bitc.fe;
|
|
dummy.bitc.bi = real.bitc.bi;
|
|
dummy.bitc.temt = real.bitc.temt;
|
|
return dummy.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LSR_dr(void)
|
|
{
|
|
GH_UART1_LSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.dr;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LSR_oe(void)
|
|
{
|
|
GH_UART1_LSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.oe;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LSR_pe(void)
|
|
{
|
|
GH_UART1_LSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.pe;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LSR_fe(void)
|
|
{
|
|
GH_UART1_LSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.fe;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LSR_bi(void)
|
|
{
|
|
GH_UART1_LSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.bi;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_LSR_temt(void)
|
|
{
|
|
GH_UART1_LSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_LSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.temt;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register UART1_MSR (read) */
|
|
/*----------------------------------------------------------------------------*/
|
|
GH_INLINE U32 GH_UART1_get_MSR(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S real;
|
|
GH_UART1_MSR_S dummy;
|
|
dummy.all = 0;
|
|
real.all = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
dummy.bitc.dcts = real.bitc.dcts;
|
|
dummy.bitc.ddsr = real.bitc.ddsr;
|
|
dummy.bitc.teri = real.bitc.teri;
|
|
dummy.bitc.ddcd = real.bitc.ddcd;
|
|
dummy.bitc.cts = real.bitc.cts;
|
|
dummy.bitc.dsr = real.bitc.dsr;
|
|
dummy.bitc.ri = real.bitc.ri;
|
|
dummy.bitc.dcd = real.bitc.dcd;
|
|
return dummy.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_dcts(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.dcts;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_ddsr(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.ddsr;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_teri(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.teri;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_ddcd(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.ddcd;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_cts(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.cts;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_dsr(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.dsr;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_ri(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.ri;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_MSR_dcd(void)
|
|
{
|
|
GH_UART1_MSR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_MSR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.dcd;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register UART1_SCR (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
GH_INLINE void GH_UART1_set_SCR(U32 data)
|
|
{
|
|
GH_UART1_SCR_REAL_S real;
|
|
GH_UART1_SCR_S dummy;
|
|
dummy.all = data ;
|
|
real.bitc.scr = dummy.bitc.scr;
|
|
*(volatile U32 *)REG_UART1_SCR_REAL = real.all;
|
|
}
|
|
GH_INLINE U32 GH_UART1_get_SCR(void)
|
|
{
|
|
GH_UART1_SCR_REAL_S real;
|
|
GH_UART1_SCR_S dummy;
|
|
dummy.all = 0;
|
|
real.all = (*(volatile U32 *)REG_UART1_SCR_REAL);
|
|
|
|
dummy.bitc.scr = real.bitc.scr;
|
|
return dummy.all;
|
|
}
|
|
GH_INLINE void GH_UART1_set_SCR_scr(U8 data)
|
|
{
|
|
GH_UART1_SCR_REAL_S d;
|
|
d.all = *(volatile U32 *)REG_UART1_SCR_REAL;
|
|
d.bitc.scr = data;
|
|
*(volatile U32 *)REG_UART1_SCR_REAL = d.all;
|
|
}
|
|
GH_INLINE U8 GH_UART1_get_SCR_scr(void)
|
|
{
|
|
GH_UART1_SCR_REAL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_UART1_SCR_REAL);
|
|
|
|
tmp_value.all = value;
|
|
return tmp_value.bitc.scr;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* init function */
|
|
/*----------------------------------------------------------------------------*/
|
|
GH_INLINE void GH_UART1_init(void)
|
|
{
|
|
GH_UART1_set_THR((U32)0x00000000);
|
|
GH_UART1_set_DLL((U32)0x00000000);
|
|
GH_UART1_set_IER((U32)0x00000000);
|
|
GH_UART1_set_DLH((U32)0x00000000);
|
|
GH_UART1_set_FCR((U32)0x00000000);
|
|
GH_UART1_set_LCR((U32)0x00000000);
|
|
GH_UART1_set_MCR((U32)0x00000000);
|
|
GH_UART1_set_SCR((U32)0x00000000);
|
|
/* read read-clear registers in order to set mirror variables */
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* end of file */
|
|
/*----------------------------------------------------------------------------*/
|
|
|